AMD Geode LX 600@0.7W Data Book page 223

Processors
Table of Contents

Advertisement

GeodeLink™ Memory Controller Register Descriptions
6.2.2
GLMC Specific MSRs
6.2.2.1
Row Addresses Bank0 DIMM0, Bank1 DIMM0 (MC_CF_BANK01)
MSR Address
20000010h
Type
RO
Reset Value
xxxxxxxx_xxxxxxxxh
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
Bit
Name
63:54
RSVD
53:32
MC_CF_BANK1
31:22
RSVD
21:0
MC_CF_BANK0
6.2.2.2
Row Addresses Bank2 DIMM0, Bank3 DIMM0 (MC_CF_BANK23)
MSR Address
20000011h
Type
RO
Reset Value
xxxxxxxx_xxxxxxxxh
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
Bit
Name
63:54
RSVD
53:32
MC_CF_BANK3
31:22
RSVD
21:0
MC_CF_BANK2
AMD Geode™ LX Processors Data Book
MC_CF_BANK01 Register Map
MC_CF_BANK01 Bit Descriptions
Description
Reserved. Reads back as 0.
Memory Configuration Back 1. Open row address (31:10) for Bank1, DIMM0.
Reserved. Reads back as 0.
Memory Configuration Back 0. Open row address (31:10) for Bank0, DIMM0.
MC_CF_BANK23 Register Map
MC_CF_BANK23
Description
Reserved. Reads back as 0.
Memory Controller Configuration Bank 3. Open row address (31:10) for Bank3,
DIMM0.
Reserved. Reads back as 0.
Memory Controller Configuration Bank 2. Open row address (31:10) for Bank2,
DIMM0.
MC_CF_BANK1
9
MC_CF_BANK0
MC_CF_BANK3
9
MC_CF_BANK2
escriptions
Bit D
33234H
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
0
223

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents