AMD Geode LX 600@0.7W Data Book page 355

Display Controller Register Descriptions
6.6.16 VGA Block Configuration Registers
6.6.16.1 VGA Configuration (VGA_CONFIG)
DC Memory Offset 100h
Type R/W
Reset Value 00000000h
This register controls palette write operations.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
31:1 RSVD
0 WPPAL
6.6.16.2 VGA Status (VGA_STATUS)
DC Memory Offset 104h
Type RO
Reset Value 00000000h
This register provides status information for the individual SMI events enabled in the VGA_CONFIG register (DC Memory
Offset 100h), as well as certain other status bits. Reading this register clears all active events.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD BLINK_CNT
Bit Name
31:30 RSVD
29:24 BLINK_CNT
23:22 RSVD
21:12 V_CNT
11:6 RSVD
5 VSYNC
4 DISPEN
3 CRTCIO_SMI
AMD Geode™ LX Processors Data Book
VGA_CONFIG Register Map
RSVD
VGA_CONFIG Bit Descriptions
Description
Reserved. Set to 0.
Write Protect Palette. If set to 1, VGA palette write operations are NOT written to the
palette RAMs. Palette writes behave normally, except that the data is discarded.
VGA_STATUS Register Map
RSVD V_CNT
VGA_STATUS Bit Descriptions
Description
Reserved.
Blink Counter Value. Unsynchronized, used as a simulation aid.
Reserved.
Vertical Counter Value. Unsynchronized, used as a simulation aid.
Reserved.
VSYNC. 1 If VSYNC is active (copy of bit 3 of ISR1).
Display Enable. 0 if both horizontal and vertical display enable are active (copy of bit 0
of ISR1).
CRTC Register SMI. If = 1, an SMI was generated due to an I/O read or write to an non-
implemented CRTC register.
33234H
9 8 7 6 5 4 3
9 8 7 6 5 4 3
RSVD
2 1 0
2 1 0
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