AMD Geode LX 600@0.7W Data Book page 545

GeodeLink™ Control Processor Register Descriptions
6.14.2 GLCP Specific MSRs - GLCP Control MSRs
6.14.2.1 GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)
MSR Address 4C000008h
Type R/W
Reset Value 00000000_00000000h
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
Bit Name
63:24 RSVD
23:0 CLK_DELAY
6.14.2.2 GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)
MSR Address 4C000009h
Type R/W
Reset Value 00000000_00000000h
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
63:34 RSVD
33 VIPVIP
32 VIPGLIU
31 AES
30 AESGLIU
29 AESEE
AMD Geode™ LX Processors Data Book
GLCP_CLK_DIS_DELAY Register Map
RSVD
GLCP_CLK_DIS_DELAY Bit Descriptions
Description
Reserved. Write as read.
Clock Disable Delay. If enabled in GLCP_GLB_PM (CLK_DLY_EN bit, MSR
4C00000Bh[4] = 1), indicates the period to wait from SLEEP_REQ before gating off
clocks specified in GLCP_PMCLKDISABLE (MSR 4C000009h). If this delay is enabled,
it overrides or disables the function of GLCP_CLK4ACK (MSR 4C000013h). If the
CLK_DLY_EN bit is not set, but this register is non-zero, then this register serves as a
timeout for the CLK4ACK behavior.
GLCP_PMCLKDISABLE Register Map
RSVD
GLCP_PMCLKDISABLE Bit Descriptions
Description
Reserved.
VIP VIPCLK Off. When set, disables VIP VIPCLK.
VIP GLIU Clock Off. When set, disables VIP GLIU clock.
AES Core Functional Clock Off. When set, disables AES encryption/decryption
clock.
AES GLIU Clock Off. When set, disables AES GLIU interface clock.
AES EEPROM Clock Off. When set, disables AES EEPROM clock.
33234H
9 8 7 6
CLK_DELAY
9 8 7 6
5 4 3 2 1 0
5 4 3 2 1 0
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