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Geode LX 700@0.8W
AMD Geode LX 700@0.8W Manuals
Manuals and User Guides for AMD Geode LX 700@0.8W. We have
1
AMD Geode LX 700@0.8W manual available for free PDF download: Data Book
AMD Geode LX 700@0.8W Data Book (680 pages)
Processors
Brand:
AMD
| Category:
Computer Hardware
| Size: 5.78 MB
Table of Contents
Table of Contents
3
List of Figures
5
List of Tables
7
1 0Overview
11
General Description
11
Figure 1-1. Internal Block Diagram
11
Features
12
2 0Architecture Overview
15
CPU Core
15
Geodelink™ Control Processor
16
Geodelink™ Interface Units
16
Geodelink™ Memory Controller
16
Graphics Processor
17
Table 2-1. Graphics Processor Feature Comparison
17
Display Controller
18
Video Processor
18
Video Input Port
18
Geodelink™ PCI Bridge
18
Security Block
19
3 0Signal Definitions
21
Figure 3-1. Signal Groups
21
Table 3-1. Video Signal Definitions Per Mode
22
Buffer Types
23
Table 3-2. Buffer Type Characteristics
23
Ball Assignments
24
Bootstrap Options
24
Table 3-3. Bootstrap Options
24
Table 3-4. Ball Type Definitions
24
Figure 3-2. BGU481 Ball Assignment Diagram
25
Table 3-5. Ball Assignments - Sorted by Ball Number
26
Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name
30
Signal Descriptions
33
Table 3-7. Signal Behavior During and after Reset
43
4 0Geodelink™ Interface Unit
45
MSR Set
45
Table 4-1. MSR Addressing
45
Figure 4-1. Geodelink™ Architecture
46
Table 4-2. MSR Mapping
47
Table 4-3. GLIU Memory Descriptor Address Hit and Routing Description
48
Table 4-4. GLIU I/O Descriptor Address Hit and Routing Description
49
GLIU Register Descriptions
50
Table 4-5. Geodelink™ Device Standard Msrs Summary
50
Table 4-6. GLIU Specific Msrs Summary
50
Table 4-7. GLIU Statistic and Comparator Msrs Summary
51
Table 4-8. GLIU P2D Descriptor Msrs Summary
53
Table 4-9. GLIU Reserved Msrs Summary
53
Table 4-10. GLIU IOD Descriptor Msrs Summary
54
5 0CPU Core
89
Core Processor Initialization
89
Table 5-1. Initialized Core Register Controls
89
Instruction Set Overview
90
Application Register Set
91
Table 5-2. Application Register Set
91
Table 5-3. Segment Register Selection Rules
92
Table 5-4. EFLAGS Register
93
System Register Set
94
Table 5-5. System Register Set
94
Table 5-6. Control Registers Map
95
Table 5-7. CR4 Bit Descriptions
96
Table 5-8. CR3 Bit Descriptions
96
Table 5-9. CR2 Bit Descriptions
96
Table 5-10. CR0 Bit Descriptions
96
Table 5-11. Effects of Various Combinations of EM, TS, and MP Bits
98
CPU Core Register Descriptions
99
Table 5-12. Standard Geodelink™ Device Msrs Summary
99
Table 5-13. CPU Core Specific Msrs Summary
99
Table 5-14. XC_HIST_MSR Exception Types
126
Table 5-15. Region Properties Register Map
170
Table 5-16. Read Operations Vs. Region Properties
170
Table 5-17. Write Operations Vs. Region Properties
170
6 0Integrated Functions
209
Figure 6-1. Integrated Functions Block Diagram
209
Geodelink™ Memory Controller
210
Figure 6-2. GLMC Block Diagram
210
Figure 6-3. HOI Addressing Example
211
Figure 6-4. HOI Example
211
Figure 6-5. LOI Addressing Example
212
Figure 6-6. LOI Example
212
Table 6-1. LOI - 2 Dimms, same Size, 1 DIMM Bank
213
Table 6-2. LOI - 2 Dimms, same Size, 2 DIMM Banks
213
Table 6-3. Non-Auto LOI - 1 or 2 Dimms, Different Sizes, 1 DIMM Bank
214
Table 6-4. Non-Auto LOI - 1 or 2 Dimms, Different Sizes, 2 DIMM Banks
214
Figure 6-7. Request Pipeline
215
Figure 6-8. DDR Reads
216
Figure 6-9. DDR Writes
217
Geodelink™ Memory Controller Register Descriptions
219
Table 6-5. Standard Geodelink™ Device Msrs Summary
219
Table 6-6. GLMC Specific MSR Summary
219
Graphics Processor
237
Figure 6-10. Graphics Processor Block Diagram
237
Table 6-7. Graphics Processor Feature Comparison
238
Table 6-8. BLT Command Buffer Structure
239
Table 6-9. Vector Command Buffer Structure
240
Table 6-10. LUT (Lookup Table) Load Command Buffer Structure
240
Table 6-11. Data Only Command Buffer Structure
240
Table 6-12. Bit Descriptions
241
Table 6-13. Pixel Ordering for 4-Bit Pixels
243
Figure 6-11. 14-Bit Repeated Pattern
244
Table 6-14. Example Vector Pattern
244
Table 6-15. Example Vector Length
244
Table 6-16. Example of Monochrome Pattern
247
Table 6-17. Example of 8-Bit Color Pattern (3:3:2 Format)
248
Table 6-18. Example of 16-Bit Color Pattern (5:6:5 Format)
248
Table 6-19. 32-Bpp 8:8:8:8 Color Data Format
249
Table 6-20. 16-Bpp Color Data Format
249
Table 6-21. 8-Bpp 3:3:2 Color Data Format
249
Table 6-22. Monochrome Data Format
249
Table 6-23. Example of Byte-Packed Monochrome Source Data
250
Table 6-24. Example of Unpacked Monochrome Source Data
250
Table 6-25. GP_RASTER_MODE Bit Patterns
251
Table 6-26. Common Raster Operations
251
Table 6-27. Alpha Blending Modes
252
Graphics Processor Register Definitions
254
Table 6-28. Standard Geodelink™ Device Msrs Summary
254
Table 6-29. Graphics Processor Configuration Register Summary
254
Table 6-30. PAT_COLOR Usage for Color Patterns
264
Table 6-31. PAT_DATA Usage for Color Patterns
265
Display Controller
278
Figure 6-12. Display Controller High-Level Block Diagram
278
Figure 6-13. GUI Block Diagram
279
Figure 6-14. VGA Block Diagram
280
Table 6-32. Display Modes
281
Table 6-33. Cursor Display Encodings
283
Table 6-34. Icon Display Encodings
283
Table 6-35. Cursor/Color Key/Alpha Interaction
284
Table 6-36. Video Bandwidth
286
Table 6-37. YUV 4:2:0 Video Data Ordering
287
Table 6-38. YUV 4:2:2 Video Data Ordering
287
Figure 6-15. VGA Frame Buffer Organization
288
Table 6-39. VGA Text Modes
288
Table 6-40. Text Mode Attribute Byte Format
288
Table 6-41. VGA Graphics Modes
288
Figure 6-16. Graphics Controller High-Level Diagram
289
Figure 6-17. Write Mode Data Flow
290
Figure 6-18. Read Mode Data Flow
291
Figure 6-19. Color Compare Operation
292
Figure 6-20. Graphics Filter Block Diagram
293
Figure 6-21. Flicker Filter and Line Buffer Path
295
Table 6-42. Programming Image Sizes
297
Figure 6-22. Interlaced Timing Settings
298
Table 6-43. Vertical Timing in Number of Lines
298
Table 6-44. Timing Register Settings for Interlaced Modes
299
Display Controller Register Descriptions
300
Table 6-45. Standard Geodelink™ Device Msrs Summary
300
Table 6-46. DC Specific Msrs Summary
300
Table 6-47. DC Configuration Control Register Summary
300
Table 6-48. VGA Block Configuration Register Summary
303
Table 6-49. VGA Block Standard Register Summary
303
Table 6-50. VGA Block Extended Register Summary
304
Table 6-51. VGA Sequencer Registers Summary
358
Table 6-52. Font Table
360
Table 6-53. CRTC Register Settings
361
Table 6-54. CRTC Registers Summary
362
Table 6-55. CRTC Memory Addressing Modes
371
Table 6-56. Graphics Controller Registers Summary
373
Table 6-57. Attribute Controller Registers Summary
378
Table 6-58. Video DAC Registers Summary
382
Table 6-59. Extended Registers Summary
384
Video Processor
388
Figure 6-23. Video Processor Block Diagram
389
Figure 6-24. Video Processor Block Diagram
390
Figure 6-25. Downscaler Block Diagram
392
Figure 6-26. Linear Interpolation Calculation
393
Figure 6-27. Mixer Block Diagram
395
Figure 6-28. Color Key and Alpha-Blending Logic
396
Table 6-60. Truth Table for Alpha-Blending
397
Figure 6-29. VOP Internal Block Diagram
398
Figure 6-30. 525-Line NTSC Video Window
399
Figure 6-31. HBLANK and VBLANK for Lines 20-262, 283-524
399
Figure 6-32. HBLANK and VBLANK for Lines 263, 525
400
Figure 6-33. HBLANK and VBLANK for Lines 1-18, 264-281
400
Figure 6-34. HBLANK and VBLANK for Lines 19, 282
400
Table 6-61. VOP Mode
401
Table 6-62. SAV/EAV Sequence
402
Table 6-63. Protection Bit Values
402
Figure 6-35. BT.656 8/16 Bit Line Data
403
Table 6-64. SAV VIP Flags
404
Table 6-65. VOP Clock Rate
404
Figure 6-36. Flat Panel Display Controller Block Diagram
405
Table 6-66. Panel Output Signal Mapping
406
Figure 6-37. Dithered 8X8 Pixel Pattern
408
Figure 6-38. N-Bit Dithering Pattern Schemes
409
Table 6-67. Register Settings for Dither Enable/Disable Feature
410
Table 6-68. Display RGB Modes
411
Video Processor Register Descriptions
412
Table 6-69. Standard Geodelink™ Device Msrs Summary
412
Table 6-70. Video Processor Module Specific Msrs Summary
412
Table 6-71. Video Processor Module Configuration Control Registers Summary
412
Video Input Port
462
Table 6-72. VIP Capabilities
462
Figure 6-39. VIP Block Diagram
463
Table 6-73. SAV/EAV Sequence
466
Figure 6-40. BT.656, 8/16-Bit Line Data
467
Figure 6-41. 525 Line, 60 Hz Digital Vertical Timing
468
Figure 6-42. Ancillary Data Packets
469
Figure 6-43. Message Passing Data Packet
470
Figure 6-44. Data Streaming Data Packet
470
Figure 6-45. BT.601 Mode Default Field Detection
471
Figure 6-46. BT.601 Mode Programmable Field Detection
472
Figure 6-47. BT.601 Mode Horizontal Timing
472
Figure 6-48. BT.601 Mode Vertical Timing
473
Figure 6-49. YUV 4:2:2 to YUV 4:2:0 Translation
474
Table 6-74. VIP Data Types / Memory Registers
475
Figure 6-50. Dual Buffer for Message Passing and Data Streaming Modes
476
Figure 6-51. Example VIP YUV 4:2:2 SAV/EAV Packets Stored in System Memory in a Linear Buffer
477
Figure 6-52. Example VIP YUV 4:2:0 Planar Buffer
478
Figure 6-53. Example VIP 8/16- and 10-Bit Ancillary Packets Stored in System Memory
479
Video Input Port Register Descriptions
482
Table 6-75. Standard Geodelink™ Device Msrs Summary
482
Table 6-76. VIP Configuration/Control Registers Summary
482
Security Block
510
Figure 6-54. Security Block Diagram
510
Table 6-77. EEPROM Address Map
512
Security Block Register Descriptions
513
Table 6-78. Standard Geodelink™ Device Msrs Summary
513
Table 6-79. Security Block Specific Msrs
513
Table 6-80. Security Block Configuration/Control Registers Summary
513
Geodelink™ Control Processor
533
Figure 6-55. GLCP Block Diagram
533
Table 6-81. TAP Control Instructions (25-Bit IR)
534
Table 6-82. TAP Instruction Bits
534
Figure 6-56. Processor Clock Generation
536
Figure 6-57. GIO Interface Block Diagram
537
Table 6-83. GIO_PCI Outputs
537
Table 6-84. CIS Signaling Protocol
538
Geodelink™ Control Processor Register Descriptions
539
Table 6-85. Standard Geodelink™ Device Msrs Summary
539
Table 6-86. GLCP Specific Msrs Summary
539
Table 6-87. Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 = 0)
556
Table 6-88. Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 Vary)
557
Geodelink™ PCI Bridge
566
Figure 6-58. GLPCI Block Diagram
566
Figure 6-59. Atomic MSR Accesses Across the PCI Bus
568
Table 6-89. Format for Accessing the Internal PCI Configuration Registers
569
Figure 6-60. Simple Round-Robin
570
Figure 6-61. Weighted Round-Robin
570
Table 6-90. PCI Device to AD Bus Mapping
570
Geodelink™ PCI Bridge Register Descriptions
572
Table 6-91. Standard Geodelink™ Device Msrs Summary
572
Table 6-92. GLPCI Specific Registers Summary
572
Table 6-93. Region Properties
586
7 0Electrical Specifications
597
Electrical Connections
597
Absolute Maximum Ratings
597
Table 7-1. Absolute Maximum Ratings
597
Operating Conditions
598
Table 7-2. Operating Conditions
598
DC Current
599
Figure 7-1. VMEMLX Power Split
600
Table 7-3. AMD Geode LX 900@1.5W Processor DC Currents
600
Table 7-4. AMD Geode LX 800@0.9W Processor DC Currents
601
Table 7-5. AMD Geode LX 700@0.8W Processor DC Currents
602
Table 7-6. AMD Geode LX 600@0.7W Processor DC Currents
603
DC Characteristics
604
Table 7-7. DC Characteristics
604
AC Characteristics
607
Figure 7-2. Drive Level and Measurement Points for Switching Characteristics
607
Figure 7-3. Drive Level and Measurement Points for Switching Characteristics
608
Table 7-8. System Interface Signals
608
Figure 7-4. Power up Sequencing
609
Figure 7-5. Drive Level and Measurement Points for Switching Characteristics
609
Table 7-9. PCI Interface Signals
609
Figure 7-6. Drive Level and Measurement Points for Switching Characteristics
610
Table 7-10. VIP Interface Signals
610
Figure 7-7. Drive Level and Measurement Points for Switching Characteristics
611
Table 7-11. Flat Panel Interface Signals
611
Table 7-12. CRT Interface Signals
612
Table 7-13. CRT Display Recommended Operating Conditions
612
Table 7-14. CRT Display Analog (DAC) Characteristics
613
Table 7-15. Memory (DDR) Interface Signals
614
Figure 7-8. DDR Write Timing Measurement Points
615
Figure 7-9. DDR Read Timing Measurement Points
616
Table 7-16. JTAG Interface Signals
617
8 0Instruction Set
619
General Instruction Set Format
619
Table 8-1. General Instruction Set Format
619
Table 8-2. Instruction Fields
620
Table 8-3. Instruction Prefix Summary
620
Table 8-4. W Field Encoding
621
Table 8-5. D Field Encoding
621
Table 8-6. S Field Encoding
621
Table 8-7. Eee Field Encoding
622
Table 8-8. Mod R/M Field Encoding
622
Table 8-9. General Registers Selected by Mod R/M Fields and W Field
623
Table 8-10. Reg Field
624
Table 8-11. Sreg2 Field Encoding
624
Table 8-12. Sreg3 Field (FS and GS Segment Register Selection)
624
Table 8-13. Ss Field Encoding
625
Table 8-14. Index Field Encoding
625
Table 8-15. Mod Base Field Encoding
626
CPUID Instruction Set
627
Table 8-16. CPUID Instruction with EAX = 00000000H
627
Table 8-17. CPUID Instruction with EAX = 00000001H
627
Table 8-18. CPUID Instruction Codes with EAX = 00000000
628
Table 8-19. CPUID Instruction with EAX = 80000000H
629
Table 8-20. CPUID Instruction with EAX = 80000001H
629
Table 8-21. CPUID Instruction Codes with EAX = 80000001H
630
Table 8-22. CPUID Instruction with EAX = 80000002H, 80000003H, or 80000004H
631
Table 8-23. CPUID Instruction with EAX = 80000005H
632
Table 8-24. CPUID Instruction with EAX = 80000006H
632
Processor Core Instruction Set
633
Table 8-25. Processor Core Instruction Set Table Legend
633
Table 8-26. Processor Core Instruction Set
634
MMX™, FPU, and AMD 3Dnow!™ Technology Instructions Sets
658
Table 8-27. MMX™, FPU, and AMD 3Dnow!™ Instruction Set Table Legend
658
Table 8-28. MMX™ Instruction Set
660
Table 8-29. FPU Instruction Set
667
Table 8-30. AMD 3Dnow!™ Technology Instruction Set
671
9 0Package Specifications
675
Physical Dimensions
675
Figure 9-1. BGU481 Top/Side View/Dimensions
675
Figure 9-2. BGU481 Bottom View/Dimensions
676
Appendix Asupport Documentation
677
Order Information
677
A.1 Order Information
677
Figure A-1. AMD Geode™ LX Processors OPN Example
677
Table A-1. Valid OPN Combinations
678
Data Book Revision History
679
Revision History
679
Table A-2. Revision History
679
Table A-3. Edits to Current Revision
679
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