AMD Geode LX 600@0.7W Data Book page 275

Graphics Processor Register Definitions
6.4.2.23 Width/Height (GP_CH3_WIDHI)
GP Memory Offset 68h
Type R/W
Reset Value 00000000h
This register is used to specify the width and the height of the bitmap to be fetched on channel 3 in pixels. This need not
match the destination width and height, as in the case of a rotation BLT where the width and height are swapped, but the
total number of pixels should be equal to the number of pixels in the destination.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
Bit Name
31:28 RSVD
27:16 WID
15:12 RSVD
11:0 HI
6.4.2.24 Host Source (GP_CH3_HSRC)
GP Memory Offset 6Ch
Type WO
Reset Value xxxxxxxxh
This register is used by software to load channel 3 data when the channel 3 pattern mode bit is not set, the channel 3
enable bit is set, and the channel 3 host source bit is set.This register is also aliased to the address range 400h-FFFh
allowing the processor to load large blocks of data to the GP using the repeat MOVS instruction.
31 30 29 28 27 26 25
Bit Name
31:0 HST_SRC
AMD Geode™ LX Processors Data Book
GP_CH3_WIDHI Register Map
WID
GP_CH3_WIDHI Bit Descriptions
Description
Reserved. Write as read.
Width. Width in pixels of the BLT operation.
Reserved. Write as read.
Height. Height in pixels of the BLT operation.
GP_CH3_HSRC Register Map
24 23 22 21 20 19 18
GP_CH3_HSRC Bit Descriptions
Description
Host Source Data. Used during BLT in host source mode
RSVD
17 16 15 14 13 12 11 10
HST_SRC
33234H
9 8 7 6 5 4 3 2
HI
9 8 7 6 5 4 3 2
1 0
1 0
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