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AMD Geode™ LX Processor
DDR2 BIOS Porting Guide
1.0
Scope
The AMD Geode™ LX processor has an integrated DDR
memory controller. Due to the concerns over the availability
and increasing cost of DDR, AMD has developed a method
for operating DDR2 memory with the processor's memory
controller. This application note details the software
changes necessary to enable this technology.
Note: The solution described in this document does not
conform to the JEDEC DDR2 Specification. This
solution may not work with all DDR2 memory.
Note: This is revision B of this document. The change
from revision A (also dated March 2009) is "AMD
Confidential" was removed.
2.0
Description
Initializing DDR2 SDRAM requires writing to additional
mode registers. In addition to the Mode Register (MR) and
Extended Mode Register (EMR), DDR2 defines two new
Extended Mode Registers, EMR(2) and EMR(3). The EMR
is renamed as EMR(1). Furthermore, the MR and EMR
definitions are not an exact match between DDR and
DDR2. Table 2-1 shows a comparison of the typical initial-
ization steps for DDR vs. DDR2.
Addressing MR vs. EMR(1), EMR(2) or EMR(3) is deter-
mined by the states of BA[2:0] while the LOAD MODE com-
mand is presented on the control signals. The data written
to the registers is the pattern presented on A[15:0] when
the command is initiated. (Note, however, that A[15:13]=0,
and BA[2]=0 in all cases.)
Software on the LX processor issues LOAD MODE com-
mands by writing the MC_CF07_DATA register. During the
operation, the memory controller (MC) uses various bits
and fields in the MC_CF07_DATA and MC_CF8F_DATA
registers. With the available settings, the LX processor is
not capable of generating the necessary signal patterns for
all the required LOAD MODE commands.
46959A - March 2009
Table 2-1. Initialization Steps
DDR
Wait a minimum of 200µs
after clocks and power are
stable, then assert CKE.
Wait a minimum of 400ns,
then issue a PRE-
CHARGE ALL command.
Issue a LOAD MODE
command to EMR to
enable the DLL.
Issue LOAD MODE com-
mand to MR with DLL
reset.
Wait at least 200 clock
cycles. Issue a PRE-
CHARGE ALL command.
Issue two REFRESH
commands.
Issue LOAD MODE to MR
without DLL reset.
SDRAM initialization is
complete.
DDR2
Wait a minimum of 200µs
after clocks and power are
stable, then assert CKE.
Wait a minimum of 400ns,
then issue a PRE-
CHARGE ALL command.
Issue a LOAD MODE
command to EMR(2)
Issue a LOAD MODE
command to EMR(3).
Issue a LOAD MODE
command to EMR(1) to
enable the DLL.
Issue LOAD MODE com-
mand to MR with DLL
reset.
Wait at least 200 clock
cycles. Issue a PRE-
CHARGE ALL command.
Issue two REFRESH
commands.
Issue LOAD MODE to MR
without DLL reset.
Issue LOAD MODE to
EMR(1) with OCD default.
Issue LOAD MODE to
EMR(1) with OCD exit.
SDRAM initialization is
complete.
1
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Related Manuals for AMD Geode LX CS5536
Summary of Contents for AMD Geode LX CS5536
- Page 1 The AMD Geode™ LX processor has an integrated DDR memory controller. Due to the concerns over the availability and increasing cost of DDR, AMD has developed a method for operating DDR2 memory with the processor’s memory controller. This application note details the software changes necessary to enable this technology.
- Page 2 CPLD simplifies the CPLD design and speeds up initialization. The I/O addresses selected for the AMD Geode™ LX Pro- cessor Refresh Reference Design Kit (RDK) board are AC10h and AC11h. This requires a modification to the Vir- tual PCI portion of the BIOS to identify the I/O range to an operating system.
-
Page 3: Cpld Registers
Address signal 9 A[8] Address signal 8 AMD Geode™ LX Processor DDR2 BIOS Porting Guide Prior to executing a LOAD MODE command, the BIOS sets the CPLD registers to the desired pattern. The DRAM reg- isters are programmed with the A[n] signals. The register being initialized is determined by the pattern on BA[1:0] (MR=00b, EMR(1)=01b, EMR(2)=10b and EMR(3)=11b). - Page 4 The reader is encouraged to have a copy of the JEDEC standard for DDR2 SDRAM, including the SPD byte definitions. The AMD Geode™ LX Processors Data Book, order# 33234, is also recom- mended. The chapters for the memory controller and GeodeLink™...
- Page 5 The memory controller is now set up correctly, and is pre- pared for turning on the memory. Now follow the DDR2 memory initialization steps (as outlined Table 2-1 on page AMD Geode™ LX Processor DDR2 BIOS Porting Guide 3.3.2 SDRAM Initialization CKE may have already been asserted, due to the requirement of the On-DIMM CPLD.
- Page 6 Next, in MC_CF07_DATA register, set MSR_BA=01b and PROG_DRAM=1. Then clear PROG_DRAM. Issue a LOAD MODE command to MR to reset the DLL. Regardless of whether the DLL is running, AMD does not recommend omitting this step. Some memory devices require A[8]=1 and all other A[n]=0 during this step.
- Page 7 Some DRAM modules may operate at higher frequencies by raising their supply voltage. The customer should con- sult the memory manufacturer before taking this approach. The BIOS may implement an algorithm that accounts for the higher frequency. AMD has seen only limited success with this technique.
- Page 8 Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. One AMD Place • P.O. Box 3453 • Sunnyvale, CA 94088-3453 USA • Tel: 408-749-4000 or 800-538-8450 • TWX: 910-339-9280 • TELEX: 34-6306...
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