4.0Geodelink™ Interface Unit; Msr Set; Table 4-1. Msr Addressing - AMD Geode LX 600@0.7W Data Book

GeodeLink™ Interface Unit
Many traditional architectures use buses to connect mod-
ules together, which usually requires unique addressing for
each register in every module. This requires that some kind
of house-keeping be done as new modules are designed
and new devices are created from the module set. Using
module select signals to create the unique addresses can
get cumbersome and requires that the module selects be
sourced from some centralized location.
To alleviate this issue, AMD developed an internal bus
architecture based on GeodeLink™ technology. The
GeodeLink architecture connects the internal modules of a
device using the data ports provided by GeodeLink Inter-
face Units (GLIUs). Using GLIUs, all internal module port
addresses are derived from the distinct port that the mod-
ule is connected to. In this way, a module's Model Specific
Registers (MSRs) do not have unique addresses until a
device is defined. Also, as defined by the GeodeLink archi-
tecture, a module's port address depends on the location of
the module sourcing the cycle, or source module (e.g.,
source module can be CPU Core, GLCP, and GLPCI; how-
ever, under normal operating conditions, accessing MSRs
is from the CPU Core).
Module Name
GeodeLink™ Interface Unit 0 (GLIU0)
GeodeLink Memory Controller (GLMC)
CPU Core (CPU Core)
Display Controller (DC)
Graphics Processor (GP)
GeodeLink Interface Unit 1 (GLIU1)
Video Processor (VP)
GeodeLink Control Processor (GLCP)
GeodeLink PCI Bridge (GLPCI)
Video Input Port (VIP)
Security Block (SB)
AMD Geode™ LX Processors Data Book
4.0GeodeLink™ Interface Unit
4.1
The AMD Geode™ LX processor incorporates two GLIUs
into its device architecture. Except for the configuration
registers that are required for x86 compatibility, all internal
registers are accessed through a Model Specific Register
(MSR) set. MSRs have a 32-bit address space and a 64-bit
data space. The full 64-bit data space is always read or
written when accessed.
An MSR can be read using the RDMSR instruction, opcode
0F32h. During an MSR read, the contents of the particular
MSR, specified by the ECX register, are loaded into the
EDX:EAX registers. An MSR can be written using the
WRMSR instruction, opcode 0F30h. During an MSR write,
the contents of EDX:EAX are loaded into the MSR speci-
fied in the ECX register. The RDMSR and WRMSR instruc-
tions are privileged instructions.
Table 4-1 shows the MSR port address to access the mod-
ules within the AMD Geode LX processor with the CPU
Core as the source module.

Table 4-1. MSR Addressing

GLIU
0
0
0
0
0
1
1
1
1
1
1
33234H

MSR Set

MSR Address
Port (Relative to CPU Core)
0 1000xxxxh
1 2000xxxxh
3 0000xxxxh
4 8000xxxxh
5 A000xxxxh
0 4000xxxxh
2 4800xxxxh
3 4C00xxxxh
4 5000xxxxh
5 5400xxxxh
6 5800xxxxh
4
45