Table 2-10 Dual-Link Signal Mapping For Dvi - AMD 780E Technical Reference Manual

DVI/HDMI™

Table 2-10 Dual-Link Signal Mapping for DVI

DVI Functional
Name
TX0M/P
TX1M/P
TX2M/P
Notes:
- H/VSYNC are transmitted on TX0M/P (Blue) channel during blank.
- For DVI dual-link mode, the first active data pixel is defined as pixel#0 (an even pixel), as opposed to the DVI specifications.
© 2009 Advanced Micro Devices, Inc.
Proprietary
Link 1
Data Phase Signal
Phase 1 EVEN_B0
Phase 2 EVEN_B1
Phase 3 EVEN_B2
Phase 4 EVEN_B3
Phase 5 EVEN_B4
Phase 6 EVEN_B5
Phase 7 EVEN_B6
Phase 8 EVEN_B7
Phase 9 EVEN_B8
Phase 10 EVEN_B9
Phase 1 EVEN_G0
Phase 2 EVEN_G1
Phase 3 EVEN_G2
Phase 4 EVEN_G3
Phase 5 EVEN_G4
Phase 6 EVEN_G5
Phase 7 EVEN_G6
Phase 8 EVEN_G7
Phase 9 EVEN_G8
Phase 10 EVEN_G9
Phase 1 EVEN_R0
Phase 2 EVEN_R1
Phase 3 EVEN_R2
Phase 4 EVEN_R3
Phase 5 EVEN_R4
Phase 6 EVEN_R5
Phase 7 EVEN_R6
Phase 8 EVEN_R7
Phase 9 EVEN_R8
Phase 10 EVEN_R9
Link 2
DVI Functional
Data Phase
Name
TX3M/P Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Phase 7
Phase 8
Phase 9
Phase 10
TX4M/P Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Phase 7
Phase 8
Phase 9
Phase 10
TX5M/P Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
Phase 7
Phase 8
Phase 9
Phase 10
Signal
ODD_B0
ODD_B1
ODD_B2
ODD_B3
ODD_B4
ODD_B5
ODD_B6
ODD_B7
ODD_B8
ODD_B9
ODD_G0
ODD_G1
ODD_G2
ODD_G3
ODD_G4
ODD_G5
ODD_G6
ODD_G7
ODD_G8
ODD_G9
ODD_R0
ODD_R1
ODD_R2
ODD_R3
ODD_R4
ODD_R5
ODD_R6
ODD_R7
ODD_R8
ODD_R9
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