AMD Geode LX 600@0.7W Data Book page 136

33234H
5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)
MSR Address 00001343h
Type R/W
Reset Value 00000000_FFFF0000h
DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status information
about debug conditions that have occurred. DR7 contains debug condition enables, types, and lengths. The contents of
debug registers are more easily accessed using the MOV instruction.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LEN3 TYPE3 LEN2 TYPE2 LEN1 TYPE1 LEN0 TYPE0 RSVD GD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD (FFFFh)
Bit Name
63:62 LEN3
61:60 TYPE3
59:58 LEN2
57:56 TYPE2
55:54 LEN1
53:52 TYPE1
51:50 LEN0
49:48 TYPE0
47:46 RSVD
45 GD
44:40 RSVD
39, 38 G3, L3
37, 36 G2, L2
35, 34 G1, L1
33, 32 G0, L0
31:16 RSVD
15 BT
14 BS
13 BD
12:4 RSVD
3 B3
2 B2
1 B1
0 B0
136
DR7_DR6_MSR Register Map
DR7_DR6_MSR Bit Descriptions
Description
Breakpoint 3 Length.
Breakpoint 3 Type.
Breakpoint 2 Length.
Breakpoint 2 Type.
Breakpoint 1 Length.
Breakpoint 1 Type.
Breakpoint 0 Length.
Breakpoint 0 Type.
Reserved.
Enable Global Detect Faults.
Reserved.
Breakpoint 3 Enables.
Breakpoint 2 Enables.
Breakpoint 1 Enables.
Breakpoint 0 Enables.
Reserved.
TSS T-Bit Trap Occured.
Single-Step Trap Occured.
Global Detect Fault Occured.
Reserved.
Breakpoint 3 Matched.
Breakpoint 2 Matched.
Breakpoint 1 Matched.
Breakpoint 0 Matched.
RSVD
9
BT BS BD RSVD (FFh)
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
G3 L3 G2 L2 G1 L1 G0 L0
8 7 6 5 4 3 2
B3 B2 B1 B0
1 0