AMD Geode LX 600@0.7W Data Book page 317

Display Controller Register Descriptions
6.6.3.3 DC Display Configuration (DC_DISPLAY_CFG)
DC Memory Offset 008h
Type R/W
Reset Value 00000000h
This register contains configuration bits for controlling the various display functions of the DC.
Unless otherwise noted, settings written to this register do not take effect until the start of the following frame or interlaced
field.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD
Bit Name
31:28 RSVD
27 VISL
26 RSVD
25 PALB
24 DCEN
23:20 RSVD
19:16 VFHPEL
15:12 VFHPSL
11:10 16BPP_MODE
AMD Geode™ LX Processors Data Book
DC_DISPLAY_CFG Register Map
RSVD VFHPEL
DC_DISPLAY_CFG Bit Descriptions
Description
Reserved.
Vertical Interrupt Select. Effective immediately.
0: SMI generated at start of vertical blank when VIEN is enabled (bit 5 = 1).
1: SMI generated at end of vertical sync when VIEN is enabled (bit 5 = 1).
Reserved.
PAL Bypass.
0: Graphics data is routed through palette RAM in 16, 24, and 32-bpp display modes.
1: Graphics data bypasses palette RAM in 16, 24, and 32-bpp display modes. While con-
figured in this mode, 2-bpp cursor and border overlays are supported, but the palette
entries for these items must be modified. See Section 6.6.7.1 on page 335 for more
information.
Display Center.
0: Normal active portion of scan line is qualified with DISPEN (ball AE4).
1: Border and active portions of scan line are qualified with DISPEN. This enables cen-
tering the display for flat panels.
Reserved.
Video-FIFO High Priority End Level. This field specifies the depth of the video FIFO (in
multiples of 64 bytes) at which a high priority request previously issued to the memory
controller for video data will end. This field should always be non-zero and should be
larger than the start level. Note that the settings in the DC_ARB_CFG register (DC Mem-
ory Offset 00Ch) can also affect the priority of requests. This field should be set to 0 if
video overlay is disabled.
Video-FIFO High Priority Start Level. This field specifies the depth of the video FIFO
(in multiples of 64 bytes) at which a high priority request is sent to the memory controller
to fill up the video FIFO. This field should always be non-zero and should be less than the
high-priority end level. Note that the settings in the DC_ARB_CFG register (DC Memory
Offset 00Ch) can also affect the priority of requests.
Per-Pixel Mode. Based on the number of bits per pixel (DISP_MODE bits [9:8] must
equal 01), this determines how those bits are allocated to color and alpha information:
For 16-bpp display format:
00: 16-bpp (RGB 5:6:5)
01: 15-bpp (RGB 5:5:5)
10: XRGB (ARGB 4:4:4)
11: Reserved
33234H
9 8
VFHPSL
7 6 5 4 3 2 1 0
RSVD
317