Security Block Register Descriptions; Table 6-78. Standard Geodelink™ Device Msrs Summary; Table 6-79. Security Block Specific Msrs; Table 6-80. Security Block Configuration/Control Registers Summary - AMD Geode LX 600@0.7W Data Book

Processors
Table of Contents

Advertisement

Security Block Register Descriptions

6.12
Security Block Register Descriptions
This section provides information on the registers associ-
ated with the Security Block (SB), including the Standard
GeodeLink Device (GLD) MSRs, the Security Block Spe-
cific MSRs (accessed via the RDMSR and WRMSR
instructions), and the Security Block Configuration/Control reg-
isters. Table 6-78 through Table 6-80 are register summary
Table 6-78. Standard GeodeLink™ Device MSRs Summary
MSR Address
Type
58002000h
RO
58002001h
R/W
58002002h
R/W
58002003h
R/W
58002004h
R/W
58002005h
R/W
MSR Address
Type
58002006h
R/W

Table 6-80. Security Block Configuration/Control Registers Summary

SB Memory
Offset
Type
000h
R/W
004h
R/W
008h
R/W
010h
R/W
014h
R/W
018h
R/W
020h
R/W
024h
R/W
028h
R/W
030h
WO
034h
WO
038h
WO
03Ch
WO
040h
R/W
044h
R/W
AMD Geode™ LX Processors Data Book
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management MSR
(GLD_MSR_PM)
GLD Diagnostic MSR (GLD_MSR_DIAG)

Table 6-79. Security Block Specific MSRs

Register Name
GLD Control MSR (GLD_MSR_CTRL)
Register Name
SB Control A (SB_CTL_A)
SB Control B (SB_CTL_B)
SB AES Interrupt (SB_AES_INT)
SB Source A (SB_SOURCE_A)
SB Destination A (SB_DEST_A)
SB Length A (SB_LENGTH_A)
SB Source B (SB_SOURCE_B)
SB Destination B (SB_DEST_B)
SB Length B (SB_LENGTH_B)
SB Writable Key 0 (SB_WKEY_0)
SB Writable Key 1 (SB_WKEY_1)
SB Writable Key 2 (SB_WKEY_2)
SB Writable Key 3 (SB_WKEY_3)
SB CBC Initialization Vector 0
(SB_CBC_IV_0)
SB CBC Initialization Vector 1
(SB_CBC_IV_1)
tables that include reset values and page references where
the bit descriptions are provided.
The MSR address is derived from the perspective of the
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more detail on MSR addressing.
Reset Value
00000000_001304xxh
00000000_00000000h
00000000_00000007h
00000000_00000019h
00000000_00000015h
00000000_00000000h
Reset Value
00000000_00000003h
Reset Value
00000000h
00000000h
00000007h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
33234H
Reference
Page 515
Page 515
Page 516
Page 516
Page 518
Page 518
Reference
Page 519
Reference
Page 520
Page 521
Page 522
Page 522
Page 523
Page 523
Page 524
Page 524
Page 525
Page 525
Page 526
Page 526
Page 527
Page 527
Page 528
513

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents