Table 6-31. Pat_Data Usage For Color Patterns - AMD Geode LX 600@0.7W Data Book

Graphics Processor Register Definitions
6.4.2.10 Pattern Data (GP_PAT_DATA_x)
GP Memory Offset 30h
34h
Type R/W
Reset Value 00000000h
In solid pattern mode, these registers are not used.
In monochrome pattern mode, GP_PAT_DATA_0 and GP_PAT_DATA_1 combine to hold the entire 8x8 pattern (64 bits).
GP_PAT_DATA_0[7:0] is the first line of the pattern, with bit 7 corresponding to the leftmost pixel on the screen.
GP_PAT_DATA_1[31:24] is the last line of the pattern.
In color pattern mode, these registers each hold part of the pattern according to Table 6-31.
Register
GP_PAT_DATA_0
GP_PAT_DATA_1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
31:0 PAT_DATA_x
6.4.2.11 Raster Mode (GP_RASTER_MODE)
GP Memory Offset 38h
Type R/W
Reset Value 00000000h
This register controls the manipulation of the pixel data through the graphics pipeline. Refer to section Section 6.3.10 "Ras-
ter Operations (ROP)" on page 251 for more information on the functionality of the ROP and Section 6.3.11 "Image Com-
positing Using Alpha" on page 252 for information on alpha blending and compositing. This register is byte writable to allow
modification of the ROP and other control bits without having to rewrite the BPP and FMT every time.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
BPP/FMT RSVD
AMD Geode™ LX Processors Data Book
GP_PAT_DATA_0
GP_PAT_DATA_1

Table 6-31. PAT_DATA Usage for Color Patterns

8-bpp Mode
Line 0, pixels 3-0
Line 0, pixels 7-4
GP_PAT_DATA_x Register Map
PAT_DATA_x
GP_PAT_DATA_x Bit Descriptions
Description
Pattern Data x.
Mono pattern mode: Pattern data.
Color pattern mode: Color pattern.
GP_RASTER_MODE Register Map
EN OS AS
16-bpp Mode
Line 0, pixels 1-0
Line 0, pixels 3-2
9 8
9
RSVD SI PI ST PT PM
33234H
32-bpp Mode
Line 0, pixel 0
Line 0, pixel 1
7 6 5 4 3 2 1
8 7 6 5 4 3 2
ROP/a
R
0
1 0
265