AMD Geode LX 600@0.7W Data Book page 550

33234H
Bit Name
59 SDCLK_SET
58:56 DDR_RLE
55 SDCLK_DIS
54:52 TLA1_OA
51:50 D_TLA1
49:48 D_TLA0
47:46 D_DQ_E
45:44 D_DQ_O
43:42 RSVD
41:40 D_SDCLK
39:38 D_CMD_O
37:36 D_CMS_E
35:34 D_MA_O
33:32 D_MA_E
31:30 D_PCI_O
29:28 D_PCI_E
27:26 D_DOTCLK
25:24 D_DRBG_O
23:22 D_DRGB_E
21:20 D_PCI_IN
19:18 D_TDBGI
17:16 D_VIP
15:14 D_VIPCLK
13 H_SDCLK
12:11 PLL_FD_DEL
10:6 RSVD
5 DLL_OV
4:0 DLL_OVS/RSDA
550
GLCP_DELAY_CONTROLS Bit Definition (Continued)
Description
SDCLK Setup.
0: Full SDCLK setup.
1: Half SDCLK setup for control signals.
DDR read latch enable position.
SDCLK disable [1,3,5].
0: All SDCLK output.
1: SDCLK[4,2,0] output only.
TLA hint pin output adjust.
Output delay for TLA1.
Output delay for TLA0.
Output delay for DQ, DQM - even byte lanes.
Output delay for DQ, DQM - odd byte lanes.
Reserved.
Output delay for SDCLK.
Output delay for CKE, CS, RAS, CAS, WE - odd bits.
Output delay for CKE, CS, RAS, CAS, WE - even bits.
Output delay for BA and MA - odd bits.
Output delay for BA and MA - even bits.
Output delay for pci_ad, IRQ13, SUSPA#, INTA# - odd bits.
Output delay for pci_ad, CBE#, PAR, STOP#, FRAME#, IRDY#, TRDY#, DEVSEL#,
REQ#, GNT# - even bits.
Output delay for DOTCLK.
Output delay for DRGB[31:0] - odd bits.
Output delay for DRGB[31:0], HSYNC, VSYNC, DISPEN, VDDEN, LDE_MOD - even
bits.
Input delay for AD[31:0], CBE#, PAR, STOP#, FRAME#, IRDY#, TRDY#, DEVSEL#,
REQ#, GNT#, CIS.
Input delay for TDBGI.
Input delay for VID[15:0], VIP_HSYNC, VIP_VSYNC.
Input delay for VIPCLK.
Half SDCLK hold select (for cmd addr).
1: Half SDCLK setup for MA and BA signals.
0: Full SDCLK setup.
PLL Feedback Delay.
00: No feedback delay.
11: Max feedback delay.
(01: ~350 ps, 10: ~700 ps, 11: ~1100 ps).
Reserved.
DLL Override (to DLL).
DLL Override Setting or Read Strobe Delay Adjust.
When DLL Override is 1 this is the DQS overide delay.
When DLL Override is 0 this is the offset adjust value.
GeodeLink™ Control Processor Register Descriptions
AMD Geode™ LX Processors Data Book