AMD Geode LX 600@0.7W Data Book page 61

GLIU Register Descriptions
4.2.2.2 Port Active Enable (PAE)
MSR Address GLIU0: 10000081h
GLIU1: 40000081h
Type R/W
Reset Value Boot Strap Dependent
Ports that are not implemented return 00 (RSVD). Ports that are slave only return 11. Master/Slave ports return the values
as stated.
GLIU0 will reset all PAE to 11 (ON) except that GLIU0 PAE3 resets to 00 when the debug stall bootstrap is active (CPU port
resets inactive for debug stall).
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
63:16 RSVD
15:14 PAE0
13:12 PAE7
11:10 PAE6
9:8 PAE5
7:6 PAE4
5:4 PAE3
3:2 PAE2
1:0 PAE1
AMD Geode™ LX Processors Data Book
PAE Register Map
RSVD
PAE Bit Descriptions
Description
Reserved.
Port Active Enable for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.)
00: OFF - Master transactions are disabled.
01: LOW - Master transactions limited to 1 outstanding transaction.
10: Reserved.
11: ON - Master transactions enabled with no limitations.
Port Active Enable for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.)
See bits [15:14] for decode.
Port Active Enable for Port 6. (GLIU0 = Not Used; GLIU1 = SB.)
See bits [15:14] for decode.
Port Active Enable for Port 5. (GLIU0 = GP; GLIU1 = VIP.)
See bits [15:14] for decode.
Port Active Enable for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.)
See bits [15:14] for decode.
Port Active Enable for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.)
See bits [15:14] for decode.
Port Active Enable for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
See bits [15:14] for decode.
Port Active Enable for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
See bits [15:14] for decode.
RSVD
PAE0 PAE7 PAE6
33234H
9 8 7 6 5 4 3 2
PAE5 PAE4 PAE3 PAE2
1 0
PAE1
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