AMD Geode LX 600@0.7W Data Book page 258

33234H
Bit Name
63:18 RSVD
17 AE
16 TE
15:2 RSVD
1 AM
0 TM
6.4.1.5 GLD Power Management MSR (GLD_MSR_PM)
MSR Address A0002004h
Type R/W
Reset Value 00000000_00000000h
This MSR contains the power management controls for the GP. Since there is only one clock domain within the GP, most
bits in this register are unused. This register allows the GP to be switched off by disabling the clocks to this block. If hard-
ware clock gating is enabled, the GP will turn off its clocks whenever there is no BLT busy or pending and no GLIU transac-
tions destined to the GP. A register or MSR write causes the GP to wake up temporarily to service the request, then return
to power down. A write to the GP_BLIT_MODE or GP_VECTOR_MODE registers (GP Memory Offset 40h and 3Ch
respectively) causes the GP to wake up for the duration of the requested operation. If software clock gating is enabled, a
write to the PRQ bit causes the GP to stop its clocks the next time that it is idle. It automatically wakes itself up when it is
busy again, clearing the PRQ bit.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
63:33 RSVD
32 PRQ
31:2 RSVD
1:0 PM
6.4.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
MSR Address A0002005h
Type R/W
Reset Value 00000000_00000000h
This register is reserved for internal use by AMD and should not be written to.
258
GLD_MSR_ERROR Bit Descriptions
Description
Reserved. Read returns 0.
Address Error. 1 indicates address violation. Write = 1 clears bit, write = 0 has no effect.
Type Error. 1 indicates type error. Write = 1 clears bit, write = 0 has no effect.
Reserved. Read returns 0.
Address Mask. Ignore address violations when set.
Type Mask. Ignore type violations when set.
GLD_MSR_PM Register Map
RSVD
RSVD
GLD_MSR_PM Bit Descriptions
Description
Reserved. Read returns 0.
Software Power Request. If software clock gating is enabled, disable the clocks the next
time the device is not busy. This bit is cleared when the device wakes up.
Reserved. Read returns 0.
Power Mode.
00: Disable clock gating. Clocks are always on.
01: Enable active hardware clock gating.
10: Enable software clock gating.
11: Enable hardware and software clock gating.
Graphics Processor Register Definitions
9 8 7 6 5 4 3
AMD Geode™ LX Processors Data Book
2 1 0
PM