AMD Geode LX 600@0.7W Data Book page 666

33234H
MMX™ Instructions
PXOR Bitwise XOR
MMX Register 2 to MMX Register 1
Memory to MMX Register
SFENCE Store Fence
1) This instruction must wait for the FPU pipeline to flush. Cycle count depends on what instructions are in the pipeline.
666
Table 8-28. MMX™ Instruction Set (Continued)
Opcode
0FEF [11 mm1 MMX reg 1 [qword] --- MMX reg 1 [qword], <--- logic exclusive
mm2] OR MMX reg 2 [qword]
0FEF [11 mm reg] MMX reg [qword] --- memory64 [qword], <--- logic exclusive
OR MMX reg [qword]
0FAE [mod 111 r/m]
Operation
AMD Geode™ LX Processors Data Book
Instruction Set
Clock Ct Notes
2
2