AMD Geode LX 600@0.7W Data Book page 201

CPU Core Register Descriptions
5.5.2.112 Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR)
MSR Address 00001982h
Type R/W
Reset Value 00000000_104823CFh
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD IMDATA1
Name
Bit
63:30 RSVD
29:21 IMDATA1
20:12 IMDATA0
11:6 IMTAG1
5:0 IMTAG0
5.5.2.113 Memory Subsystem Array Control 2 MSR (MSS_ARRAY_CTL2_MSR)
MSR Address 00001983h
Type R/W
Reset Value 00000104_820C30C3h
L2 delay control settings.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
L2DATA0
Bit Name
63:42 RSVD
41:33 L2DATA1
32:24 L2DATA0
23:18 L2TAG3
17:12 L2TAG2
11:6 L2TAG1
5:0 L2TAG0
AMD Geode™ LX Processors Data Book
MSS_ARRAY_CTL1_MSR Register Map
RSVD
IMDATA0
MSS_ARRAY_CTL1_MSR Bit Descriptions
Description
Reserved. (Default = 0)
Instruction Memory Subsystem Data 1 Delay Control. (Default = 82)
Instruction Memory Subsystem Data 0 Delay Control. (Default = 82)
Instruction Memory Subsystem Tag 1 Delay Control. (Default = F)
Instruction Memory Subsystem Tag 0 Delay Control. (Default = F)
MSS_ARRAY_CTL2_MSR Register Map
RSVD
L2TAG3
MSS_ARRAY_CTL2_MSR Bit Descriptions
Description
Reserved. (Default = 0)
L2 Cache Data 1 Delay Setting. (Default = 82)
L2 Cache Data 0 Delay Setting. (Default = 82)
L2 Cache Tag 3 Delay Setting. (Default = 3)
L2 Cache Tag 2 Delay Setting. (Default = 3)
L2 Cache Tag 1 Delay Setting. (Default = 3)
L2 Cache Tag 0 Delay Setting. (Default = 3)
9
IMTAG1
9
L2TAG2 L2TAG1
33234H
8 7 6 5 4 3 2
IMTAG0
L2DATA1
8 7 6 5 4 3 2
L2TAG0
1 0
1 0
201