Geodelink™ Control Processor Register Descriptions; Table 6-85. Standard Geodelink™ Device Msrs Summary; Table 6-86. Glcp Specific Msrs Summary - AMD Geode LX 600@0.7W Data Book

GeodeLink™ Control Processor Register Descriptions
6.14 GeodeLink™ Control Processor Register Descriptions
All GeodeLink Control Processor registers are Model Spe-
cific Registers (MSRs) and are accessed via the RDMSR
and WRMSR instructions.
The registers associated with the GLCP are the Standard
GeodeLink™ Device (GLD) MSRs and GLCP Specific
MSRs. Table 6-85 and Table 6-86 are register summary
Table 6-85. Standard GeodeLink™ Device MSRs Summary
MSR
Address Type
4C002000h RO
4C002001h R/W
4C002002h R/W
4C002003h R/W
4C002004h R/W
4C002005h R/W
MSR
Address Type
GLCP Control MSRs
4C000008h R/W
4C000009h R/W
4C00000Ah RO
4C00000Bh R/W
4C00000Ch R/W
4C00000Dh R/W
4C00000Eh R/W
4C00000Fh R/W
4C000010h R/W
4C000011h RO
4C000012h R/W
4C000013h R/W
4C000014h R/W
AMD Geode™ LX Processors Data Book
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management MSR
(GLD_MSR_PM)
GLD Diagnostic MSR (GLD_MSR_DIAG)

Table 6-86. GLCP Specific MSRs Summary

Register Name
GLCP Clock Disable Delay Value
(GLCP_CLK_DIS_DELAY)
GLCP Clock Mask for Sleep Request
(GLCP_PMCLKDISABLE)
Chip Fabrication Information (GLCP_FAB)
GLCP Global Power Management Controls
(GLCP_GLB_PM)
GLCP Debug Output from Chip
(GLCP_DBGOUT)
GLCP Processor Status (GLCP_PROCSTAT)
GLCP DOWSER (GLCP_DOWSER)
GLCP I/O Delay Controls
(GLCP_DELAY_CONTROLS)
GLCP Clock Control (GLCP_CLKOFF)
GLCP Clock Active (GLCP_CLKACTIVE)
GLCP Clock Mask for Debug Clock Stop
Action (GLCP_CLKDISABLE)
GLCP Clock Active Mask for Suspend
Acknowledge (GLCP_CLK4ACK)
GLCP System Reset and PLL Control
(GLCP_SYS_RSTPLL)
tables that include reset values and page references where
the bit descriptions are provided.
Note: The MSR address is derived from the perspective
of the CPU Core. See Section 4.1 "MSR Set" on
page 45 for more details on MSR addressing.
Reset Value
00000000_00002400h
00000000_00000000h
00000000_0000001Fh
00000000_00000000h
00000000_00000015h
00000000_00000000h
Reset Value
00000000_00000000h
00000000_00000000h
00000000_00000001h
00000000_00000000h
00000000 00000000h
Bootstrap Dependant
00000000_00000000h
00000000_00000000h
00000000_00000000h
Input Determined
00000000_00000000h
00000000_00000000h
Bootstrap specific
33234H
Reference
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