AMD Geode LX 600@0.7W Data Book page 135

CPU Core Register Descriptions
5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR)
MSR Address 00001340h
Type R/W
Reset Value xxxxxxxx_xxxxxxxxh
DR1_DR0_MSR provides access to Debug Register 1 (DR1) and Debug Register 0 (DR0). DR0 and DR1 each contain
either an I/O port number or a linear address for use as a breakpoint. The contents of debug registers are more easily
accessed using the MOV instruction.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
63:32 DR1
31:0 DR0
5.5.2.28 Debug Registers 3 and 2 MSR (DR3_DR2_MSR)
MSR Address 00001341h
Type R/W
Reset Value xxxxxxxx_xxxxxxxxh
DR3/DR2_MSR provides access to Debug Register 3 (DR3) and Debug Register 2 (DR2). DR2 and DR3 each contain
either an I/O port number or a linear address for use as a breakpoint. The contents of debug registers are more easily
accessed using the MOV instruction.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Name
63:32 DR3
31:0 DR2
AMD Geode™ LX Processors Data Book
DR1_DR0_MSR Register Map
DR1_DR0_MSR Bit Descriptions
Description
Breakpoint 1 I/O Port Number/Linear Address.
Breakpoint 0 I/O Port Number/Linear Address.
DR3_DR2_MSR Register Map
DR2_DR3_MSR Bit Descriptions
Description
Breakpoint 3 I/O Port Number/Linear Address.
Breakpoint 2 I/O Port Number/Linear Address.
DR1
9
DR0
DR3
9
DR2
33234H
8 7 6 5 4 3 2
8 7 6 5 4 3 2
1 0
1 0
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