AMD Geode LX 600@0.7W Data Book page 552

33234H
Bit Name
11 DCDOT_0
10 GLIU0_1
9 GLIU0_0
8 GP
7 GLMC
6 DRAM
5 BC_GLIU
4 BC_VA
3 MSS
2 IPIPE
1 FPUFAST
0 FPUSLOW
6.14.2.10 GLCP Clock Active (GLCP_CLKACTIVE)
MSR Address 4C000011h
Type RO
Reset Value Input Determined
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions.
552
GLCP_CLKOFF Bit Descriptions (Continued)
Description
DC Dot Clock Off. When set, disables DC Dot Clock 0 (DC).
GLIU0Clock Off. When set, disables main clock to primary GLIU.
GLIU0 Timer Logic Clock Off. When set, disables clock to timer logic of primary
GLIU.
GP Clock Off. When set, disables GP clock (GLIU).
GLMC Clock Off. When set, disables GLIU clock to memory controller.
DRAM Clocks Off. When set, disables external DRAM clocks (and, hence, feedback
clocks).
Bus Controller Clock Off. When set, disables clock to CPU bus controller block.
CPU to Bus Controller Clock Off. When set, disables CPU clock to bus controller
block.
CPU to MSS Clock Off. When set, disables CPU clock to MSS block.
CPU to IPIPE Clock Off. When set, disable CPU clock to IPIPE block.
FPU Fast Clock Off. When set, disables the fast FPU clock.
FPU Clock Off. When set, disables the slow CPU clock to FPU.
GLCP_CLKACTIVE Register Map
RSVD
GeodeLink™ Control Processor Register Descriptions
9 8 7 6
AMD Geode™ LX Processors Data Book
5 4 3 2 1 0