Register Block Definition; Table 6-4 Pci Status Register; Table 6-6 Power Management Register Block - AMD 780E Technical Reference Manual

Power Management for the Graphics Controller

Table 6-4 PCI Status Register

Bits Default Value
15:05 --
04 1b
03:00 0h
The location of the Capabilities Pointer (CAP_PTR) depends on the PCI header type. See PCI Specification Revision 2.2
for specification of CAP_PTR offsets.
Table 6-5 Capabilities Pointer (CAP_PTR)
Bits
07:00 50h
The graphics core implements extended capabilities of the AGP and Power Management. It needs to provide the
standardized register interface. The first entry in the chain of descriptors has to be the PMI descriptor, as this functionality
will be supported even if the RS780E operates as a PCI device. The Capabilities Identifier for Power Management is 01h.
6.2.4

Register Block Definition

This section describes the PCI Power Management Interface registers. These registers are implemented inside the Host
Interface (HI) as part of the configuration space of the device (RS780E).

Table 6-6 Power Management Register Block

Capability Identifiers (CAP_ID)
Next Item Pointer (NEXT_ITEM_PTR)
Power Management Capabilities (PMC)
Power Management Control/Status Register (PMCSR)
Reserved
The first 16 bits (Capabilities ID [offset = 0] and Next Item Pointer [offset = 1]) are used for the linked list infrastructure.
The next 32 bits (PMC [offset = 2] and PMCSR registers [offset = 4]) are required for compliance with this specification.
As with all PCI configuration registers, these registers may be accessed as bytes, 16-bit words, or 32-bit DWORDs. All of
the write operations to the reserved registers must be treated as no-ops. This implies that the access must be completed
normally on the bus and the data should be discarded. Read accesses to the reserved or the unimplemented registers must
be completed normally and a data value of 0000h should be returned.
© 2009 Advanced Micro Devices, Inc.
Proprietary
Read/
Write
--
Read Only
Read Only
Read/
Default Value
Write
Read Only
Register Fields
Refer to PCI Local Bus Specification, Revision 2.2
This bit indicates whether this function implements a list of extended capabilities
such as PCI power management. When set, this bit indicates the presence of
Capabilities. A value of 0 implies that this function does not implement
Capabilities.
Reserved
The CAP_PTR provides an offset in the PCI Configuration Space of the
function to access the location of the first item in the Capabilities linked list. The
CAP_PTR offset is DWORD aligned, so that the two least significant bits are
always zeros.
Offset
00h
01h
02h
04h
06h
Description
Description
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