11.1 Clock Output Controller Functions
The clock output controller is intended for carrier output during remote controlled transmission and clock output
for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output from the
PCL/TPO/P60 pin.
Figure 11-1 shows the clock output controller block diagram.
f
X
f
/2
X
2
f
/2
X
3
f
/2
X
4
f
/2
X
5
f
/2
X
6
f
/2
X
7
f
/2
X
3
CLOE CCS2 CCS1 CCS0
Clock output selection register (CKS)
Note TPO: Prescaler output signal of 16-bit timer 0 TM0
11.2 Clock Output Controller Configuration
The clock output controller consists of the following hardware.
Control register
CHAPTER 11 CLOCK OUTPUT CONTROLLER
Figure 11-1. Clock Output Controller Block Diagram
TPO
Clock
controller
P60
output latch
Internal bus
Table 11-1. Clock Output Controller Configuration
Item
Clock output selection register (CKS)
Port mode register 6 (PM6)
Preliminary User's Manual U14581EJ3V0UM00
Note
PM60
Port mode register 6 (PM6)
Configuration
PCL/TPO/P60
149