ST STM32G4 Series Reference Manual page 201

RM0440
31 30 29
IRH_ PG10_
Res.
EN Mode
r r
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
r r
Bits 29:28 PG10_Mode: PG10 pad mode
Bits 22:20 Reserved, must be kept at reset value.
Embedded Flash memory (FLASH) for category 2 devices
28 27 26 25
n nSW CCMSRAM
BOOT0 BOOT0 _RST
r r r
12 11 10 9
Res. BOR_LEV[2:0]
r r r
Bit 31 Reserved, must be kept at reset value.
Bit 30 IRH_IN: Internal reset holder for PG10
0: IRH disabled
1: IRH enabled
00: Reset Input/Output
01: Reset Input only
10: GPIO
11: Reset Input/Output
Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: Software BOOT0
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PB8/BOOT0 pin
Bit 25 CCMSRAM_RST: CCM SRAM erase when system reset
0: CCM SRAM erased when a system reset occurs
1: CCM SRAM is not erased when a system reset occurs
Bit 24 SRAM_PE: SRAM1 and CCM SRAM parity check enable
0: SRAM1 and CCM SRAM parity check enable
1: SRAM1 and CCM SRAM parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to
configuration.
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
24 23 22
SRAM n
Res.
_PE BOOT1
r r
8 7 6
r r r
RM0440 Rev 4
21 20 19 18
WWDG IWGD_
Res. Res.
_SW STDBY
r r
5 4 3 2
RDP[7:0]
r r r r
Section 2.6: Boot
17 16
IWDG_ IWDG_
STOP SW
r r
1 0
r r
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