ST STM32G4 Series Reference Manual page 63

RM0440
Figure 245. Fault signal filtering (FLTxF[3:0]= 0010: f
Figure 246. Fault counter cumulative mode (FLTxRSTM = 1, FLTxCNT[3:0] = 2) . . . . . . . . . . . . . . . 930
Figure 247. Auxiliary outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Figure 248. Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . . . . . . . . . . . . . . . . . . . . 933
Figure 249. Deadtime distortion on auxiliary output when exiting burst mode. . . . . . . . . . . . . . . . . . . 933
Figure 250. Counter behavior in synchronized start mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Figure 251. ADC trigger selection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Figure 252. ADC triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Figure 253. ADC trigger post-scaling in up-counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Figure 254. ADC trigger post-scaling in up/down counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Figure 255. Combining several updates on a single hrtim_dac_trgx output . . . . . . . . . . . . . . . . . . . . 941
Figure 256. DAC triggers for slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
Figure 257. DAC triggers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure 258. DMA burst overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Figure 259. Burst DMA operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 260. Registers update following DMA burst transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Figure 261. Buck converter topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Figure 262. Dual Buck converter management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 263. Synchronous rectification depending on output current . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 264. Buck with synchronous rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Figure 265. 3-phase interleaved buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Figure 266. 3-phase interleaved buck converter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Figure 267. Transition mode PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 268. Transition mode PFC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Figure 269. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Figure 270. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1092
Figure 271. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1092
Figure 272. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
Figure 273. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
Figure 274. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Figure 275. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Figure 276. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
Figure 277. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Figure 278. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
Figure 279. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Figure 280. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Figure 281. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
Figure 282. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 1100
Figure 283. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 1102
Figure 284. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
Figure 285. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1103
Figure 286. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
Figure 287. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . 1104
Figure 288. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1105
Figure 289. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1106
Figure 290. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Figure 291. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1108
Figure 292. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
Figure 293. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
Figure 294. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
= fHRTIM, N = 4) . . . . . . . . . . . . . . . 928
SAMPLING
RM0440 Rev 4
List of figures
63/2126
71