Flash Power-Down Key Register (Flash_Pdkeyr) - ST STM32G4 Series Reference Manual

Embedded Flash memory (FLASH) for category 4 devices
4.7.2

Flash Power-down key register (FLASH_PDKEYR)

Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access
31 30 29
w w w
15 14 13
w w w
Bits 31:0 PDKEYR: Power-down in Run mode Flash key
174/2126
Bit 11 ICRST: Instruction cache reset
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the instruction cache is disabled.
Bit 10 DCEN: Data cache enable
0: Data cache is disabled
1: Data cache is enabled
Bit 9 ICEN: Instruction cache enable
0: Instruction cache is disabled
1: Instruction cache is enabled
Bit 8 PRFTEN: Prefetch enable
0: Prefetch disabled
1: Prefetch enabled
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 LATENCY[3:0]: Latency
These bits represent the ratio of the SYSCLK (system clock) period to the Flash
access time.
0000: Zero wait state
0001: One wait state
0010: Two wait states
0011: Three wait states
0100: Four wait states
...1111: Fifteen wait states
28 27 26 25
w w w w
12 11 10 9
w w w w
The following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR:
PDKEY1: 0x0415 2637
PDKEY2: 0xFAFB FCFD
24 23 22
PDKEYR[31:16]
w w w
8 7 6
PDKEYR[15:0]
w w w
RM0440 Rev 4
21 20 19 18
w w w w
5 4 3 2
w w w w
RM0440
17 16
w w
1 0
w w