ST STM32G4 Series Reference Manual page 25

Advanced arm-based 32-bit mcus
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RM0440
27.5.31 HRTIM timer x external event filtering register 1 (HRTIM_EEFxR1)
27.5.32 HRTIM timer x external event filtering register 2 (HRTIM_EEFxR2)
27.5.33 HRTIM timer A reset register (HRTIM_RSTAR) . . . . . . . . . . . . . . . . . 1002
27.5.34 HRTIM timer B reset register (HRTIM_RSTBR) . . . . . . . . . . . . . . . . 1004
27.5.35 HRTIM timer C reset register (HRTIM_RSTCR) . . . . . . . . . . . . . . . . 1006
27.5.36 HRTIM timer D reset register (HRTIM_RSTDR) . . . . . . . . . . . . . . . . 1008
27.5.37 HRTIM timer E reset register (HRTIM_RSTER) . . . . . . . . . . . . . . . . 1010
27.5.38 HRTIM timer F reset register (HRTIM_RSTFR) . . . . . . . . . . . . . . . . . 1012
27.5.39 HRTIM timer x chopper register (HRTIM_CHPxR) (x = A to F) . . . . . 1014
27.5.40 HRTIM timer A capture 1 control register (HRTIM_CPT1ACR) . . . . . 1015
27.5.41 HRTIM timer B capture 1 control register (HRTIM_CPT1BCR) . . . . . 1015
27.5.42 HRTIM timer C capture 1 control register (HRTIM_CPT1CCR) . . . . 1015
27.5.43 HRTIM timer D capture 1 control register (HRTIM_CPT1DCR) . . . . 1016
27.5.44 HRTIM timer E capture 1 control register (HRTIM_CPT1ECR) . . . . . 1016
27.5.45 HRTIM timer F capture 1 control register (HRTIM_CPT1FCR) . . . . . 1016
27.5.46 HRTIM timer x capture 2 control register (HRTIM_CPT2xCR)
27.5.47 HRTIM timer x output register (HRTIM_OUTxR) (x = A to F) . . . . . . 1023
27.5.48 HRTIM timer x fault register (HRTIM_FLTxR) (x = A to F) . . . . . . . . . 1026
27.5.49 HRTIM timer x control register 2 (HRTIM_TIMxCR2) (x = A to F) . . . 1027
27.5.50 HRTIM timer x external event filtering register 3 (HRTIM_TIMxEEFR3)
27.5.51 HRTIM control register 1 (HRTIM_CR1) . . . . . . . . . . . . . . . . . . . . . . 1031
27.5.52 HRTIM control register 2 (HRTIM_CR2) . . . . . . . . . . . . . . . . . . . . . . 1033
27.5.53 HRTIM interrupt status register (HRTIM_ISR) . . . . . . . . . . . . . . . . . . 1034
27.5.54 HRTIM interrupt clear register (HRTIM_ICR) . . . . . . . . . . . . . . . . . . . 1036
27.5.55 HRTIM interrupt enable register (HRTIM_IER) . . . . . . . . . . . . . . . . . 1037
27.5.56 HRTIM output enable register (HRTIM_OENR) . . . . . . . . . . . . . . . . . 1038
27.5.57 HRTIM output disable register (HRTIM_ODISR) . . . . . . . . . . . . . . . . 1039
27.5.58 HRTIM output disable status register (HRTIM_ODSR) . . . . . . . . . . . 1040
27.5.59 HRTIM burst mode control register (HRTIM_BMCR) . . . . . . . . . . . . 1041
27.5.60 HRTIM burst mode trigger register (HRTIM_BMTRGR) . . . . . . . . . . 1043
27.5.61 HRTIM burst mode compare register (HRTIM_BMCMPR) . . . . . . . . 1045
27.5.62 HRTIM burst mode period register (HRTIM_BMPER) . . . . . . . . . . . . 1045
27.5.63 HRTIM timer external event control register 1 (HRTIM_EECR1) . . . 1046
27.5.64 HRTIM timer external event control register 2 (HRTIM_EECR2) . . . 1048
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
(x = A to F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
RM0440 Rev 4
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