I 2 C Bus - Xilinx VC707 User Manual

The VC707 board base board uses a male Samtec MTLW-107-07-G-D-265 2x7 header (J23) with
0.025-inch square posts on 0.100-inch centers for connecting to a Samtec SLW-107-01-L-D female
socket on the LCD display panel assembly. The LCD header shown in
is not installed, the J31 header pins listed in
X-Ref Target - Figure 1-21
Low Profile Socket
Samtec SLW-107-01-L-D
Low Profile Terminal
Samtec MTLW-107-07-G-D-265
Table 1-23
Table 1-23: FPGA to LCD Header Connections
References
The data sheet for the Displaytech S162DBABC LCD can be found at the Displaytech website
[Ref
2
I C Bus
[Figure
The VC707 board implements a single I
which is routed through a 1-to-8 channel I
up to 400 kHz.
The bus switch I
the desired downstream device.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Figure 1-21: LCD Header Details
lists the connections between the FPGA and the LCD header.
FPGA (U1)
Net Name
Pin
AT42 LCD_DB4_LS
AR38 LCD_DB5_LS
AR39 LCD_DB6_LS
AN40 LCD_DB7_LS
AR42 LCD_RW_LS
AN41 LCD_RS_LS
AT40 LCD_E_LS
24]. Choose the S162D model full spec download arrow.
1-2, callout 20]
2
C address is 0x74 (0b1110100) and must be addressed and configured to select
www.xilinx.com
Table 1-23 are available for use as GPIO.
LCD Display Assembly
10 mm
VC707 PWA
I/O Standard
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
2
C port on the FPGA (IIC_SDA_MAIN, IIC_SDA_SCL),
2
C bus switch (U52). The bus switch can operate at speeds
Feature Descriptions
Figure 1-21. When the LCD
UG885_c1_21_021412
LCD Header Pin
(J31)
4
3
2
1
10
11
9
49
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