Xilinx VC707 User Manual page 62

VC707 Evaluation Board Features
Chapter 1:
Table 1-27: J35 VITA 57.1 FMC HPC Connections (Cont'd)
J35
FMC 1
Schematic Net Name
HPC
Pin
C2 FMC1_HPC_DP0_C2M_P
C3 FMC1_HPC_DP0_C2M_N
C6 FMC1_HPC_DP0_M2C_P
C7 FMC1_HPC_DP0_M2C_N
C10 FMC1_HPC_LA06_P
C11 FMC1_HPC_LA06_N
C14 FMC1_HPC_LA10_P
C15 FMC1_HPC_LA10_N
C18 FMC1_HPC_LA14_P
C19 FMC1_HPC_LA14_N
C22 FMC1_HPC_LA18_CC_P
C23 FMC1_HPC_LA18_CC_N
C26 FMC1_HPC_LA27_P
C27 FMC1_HPC_LA27_N
C30 FMC1_HPC_IIC_SCL
C31 FMC1_HPC_IIC_SDA
C34 GA0 = 0 = GND
C35 VCC12_P
C37 VCC12_P
C39 VCC3V3
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J35
I/O
U1 FPGA FMC 1
Standard
Pin HPC
Pin
(1)
E2 D1
(1)
E1 D4
(1)
D8 D5
(1)
D7 D8
LVCMOS18 K42 D9
LVCMOS18 J42 D11
LVCMOS18 N38 D12
LVCMOS18 M39 D14
LVCMOS18 N39 D15
LVCMOS18 N40 D17
LVCMOS18 M32 D18
LVCMOS18 L32 D20
LVCMOS18 J31 D21
LVCMOS18 H31 D23
U52.4 D24
U52.3 D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
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Schematic Net Name
PWRCTL1_VCC4B_PG
FMC1_HPC_GBTCLK0_M2C_P
FMC1_HPC_GBTCLK0_M2C_N
FMC1_HPC_LA01_CC_P
FMC1_HPC_LA01_CC_N
FMC1_HPC_LA05_P
FMC1_HPC_LA05_N
FMC1_HPC_LA09_P
FMC1_HPC_LA09_N
FMC1_HPC_LA13_P
FMC1_HPC_LA13_N
FMC1_HPC_LA17_CC_P
FMC1_HPC_LA17_CC_N
FMC1_HPC_LA23_P
FMC1_HPC_LA23_N
FMC1_HPC_LA26_P
FMC1_HPC_LA26_N
FMC1_HPC_TCK_BUF
FMC_TDI_BUF
FMC1_TDO_FMC2_TDI
VCC3V3
FMC1_HPC_TMS_BUF
NC
GA1 = 0 = GND
VCC3V3
VCC3V3
VCC3V3
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
U1
I/O
FPGA
Standard
Pin
AL32
(1)
A10
(1)
A9
LVCMOS18 J40
LVCMOS18 J41
LVCMOS18 M41
LVCMOS18 L41
LVCMOS18 R42
LVCMOS18 P42
LVCMOS18 H39
LVCMOS18 G39
LVCMOS18 L31
LVCMOS18 K32
LVCMOS18 P30
LVCMOS18 N31
LVCMOS18 J30
LVCMOS18 H30
U19.14
U19.18
U27.2
U19.17