Xilinx VC707 User Manual page 77

For external measurements an XADC header (J19) is provided. This header can be used to provide
analog inputs to the FPGA's dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0],
VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and
Channel 8 is supported.
A user-provided analog signal multiplexer card can be used to sample additional external analog
inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines.
Figure 1-35
X-Ref Target - Figure 1-35
XADC_VCC5V0
VADJ
Table 1-33
Table 1-33: XADC Header J19 Pinout
Net Name
VN, VP
XADC_VAUX0P, N
XADC_VAUX8N, P
DXP, DXN
XADC_AGND
XADC_VREF
XADC_VCC5V0
XADC_VCC_HEADER
VADJ
GND
XADC_GPIO_3, 2, 1, 0 19, 20, 17, 18
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
shows the XADC header connections.
XADC_VN
XADC_VAUX0P
XADC_VAUX8N
XADC_DXP
XADC_VREF
XADC_GPIO_1
XADC_GPIO_3
Figure 1-35: XADC Header (J19)
describes the XADC header J19 pin functions.
J19 Pin
Number
1, 2 Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as I/O inputs when anti-alias
3, 6
capacitor is not present.
Auxiliary analog input channel 8. Also supports use as I/O inputs when anti-alias
7, 8
capacitor is not present.
9, 12 Access to thermal diode.
4, 5, 10 Analog ground reference.
11 1.25V reference from the board.
13 Filtered 5V supply from board.
14 Analog 1.8V supply for XADC.
15 VCCO supply for bank which is the source of DIO pins.
16 Digital Ground (board) Reference
Digital I/O. These pins should come from the same bank. These I/Os should not be
shared with other functions because they are required to support 3-state operation.
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J19
1 2
3 4
5 6 XADC_VAUX0N
7 8 XADC_VAUX8P
9 10
11 12
XADC_VCC_HEADER
13 14
15 16
XADC_GPIO_0
17 18
XADC_GPIO_2
19 20
GND
XADC_AGND XADC_AGND
Description
Feature Descriptions
XADC_VP
XADC_DXN
UG885_c1_32_030512
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