Xilinx VC707 User Manual page 50

VC707 Evaluation Board Features
Chapter 1:
The VC707 board I
X-Ref Target - Figure 1-22
User applications that communicate with devices on one of the downstream I
up a path to the desired bus through the U52 bus switch at I
Table 1-24
Table 1-24: I
PCA9548
Si570 Clock
FMC1 HPC
FMC2 HPC
M24C08 EEPROM
SFP Module
ADV7512 HDMI
DDR3 SODIMM
Si5324 Clock
Notes:
1. Use the PCA9458 (U52) at I
Information about the PCA9548 is available on the TI Semiconductor website
50
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2
C bus topology is shown in
U1
FPGA
Bank 15
(2.5V)
IIC_SDA/SCL_MAIN
Figure 1-22: I
lists the address for each bus.
2
C Bus Addresses
2
I C Device
2
C address 0x74 (0b1110100) to setup the path to these buses.
The PCA9548 U52 RESET_B pin 24 is connected to the FPGA U1 bank 15 pin AY42
Caution!
via level-shifter U70. The FPGA pin AY42 LVCMOS18 net IIC_MUX_RESET_B_LS must be
driven High to enable I2C bus transactions with the devices connected to U52.
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Figure 1-22.
U52
PCA9548
1 2 C 1-to-8
Bus Switch
CH0 - USER_CLK_SDL/SCL
CH1 - FMC1_HPC_IIC_SDA/SCL
CH2 - FMC2_HPC_IIC_SDA/SCL
CH3 - EEPROM_IIC_SDA/SCL
CH4 - SFP_IIC_SDA/SCL
CH5 - IIC_SDA/SCL_HDMI
CH6 - IIC_SDA/SCL_DDR3
CH7 - SI5324_SDA/SCL
2
C Bus Topology
2
C address 0x74 (0b1110100).
2
I C Switch
2
I
Position
NA
0b1110100
0
0b1011101
1
0bXXXXX00
2
0bXXXXX00
3
0b1010100
4
0b1010000
5
0b0111001
6
0b1010000, 0b0011000
7
0b1101000
UG885 (v1.8) February 20, 2019
UG855_C1_22_021012
2
C buses must first set
C Address
[Ref 25].
VC707 Evaluation Board