Virtex-7 Xc7Vx485T-2Ffg1761C Fpga - Xilinx VC707 User Manual

Virtex-7 XC7VX485T-2FFG1761C FPGA

[Figure
The VC707 board is populated with the Virtex-7 XC7VX485T-2FFG1761C FPGA.
For further information on Virtex-7 FPGAs, see 7 Series FPGAs Overview (DS180)
Series FPGAs Packaging and Pinout Product Specifications User Guide (UG475)
To determine the type of FPGA resident on the VC707 board, refer to the Master Answer Record
listed in
FPGA Configuration
The VC707 board supports two of the five 7 series FPGA configuration modes:
•
•
Each configuration interface corresponds to one or more configuration modes and bus widths as
listed in
respectively as shown in
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 010, which selects Master BPI at board power-on. See
Configuration Options
Table 1-2: VC707 Board FPGA Configuration Modes
Master BPI
JTAG
For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide (UG470)
[Ref
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
1-2, callout 1]
Appendix G: References.
Master BPI using the onboard Linear BPI Flash memory
JTAG using a type-A to micro-B USB cable for connecting the host PC to the VC707 board
configuration port
Table 1-2. The mode switches M2, M1, and M0 are on SW11 positions 3, 4, and 5
Figure 1-3.
ON Position = 1
Figure 1-3: SW11 Default Settings
for detailed information about the mode switch SW11.
Configuration SW13 DIP switch
Mode Settings (M[2:0])
3].
www.xilinx.com
1 2 3 4 5
OFF Position = 0
Bus
Width
x8, x16
010
x1
101
Feature Descriptions
[Ref 1], and 7
[Ref 14].
UG885_c1_03_020612
CCLK
Direction
Output
Not Applicable
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