Xilinx VC707 User Manual page 27

A 2-mm JTAG header (J4) is also provided in parallel for access by Xilinx download cables such as
the Platform Cable USB II and the Parallel Cable IV.
The JTAG chain of the VC707 board is illustrated in
any time regardless of FPGA mode pin settings. JTAG initiated configuration takes priority over the
configuration method selected through the FPGA mode pin settings at SW11.
X-Ref Target - Figure 1-7
USB
Module (U26)
or
JTAG
Connector
(J4)
TDO
TDI
When an FMC mezzanine card is attached to the VC707 board it is automatically added to the JTAG
chain through electronically controlled single-pole single-throw (SPST) switches U27 and U28. The
SPST switches are in a normally closed state and transition to an open state when an FMC
mezzanine card is attached. Switch U27 adds an attached FMC1 HPC mezzanine card to the FPGAs
JTAG chain as determined by the FMC_HPC_PRSNT_M2C_B signal. Switch U28 adds an
attached FMC2 HPC mezzanine card to the FPGAs JTAG chain as determined by the
FMC2_LPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO
connection via a device or bypass jumper to ensure that the JTAG chain connects to the FPGA U1.
The JTAG connectivity on the VC707 board allows a host computer to download bitstreams to the
FPGA using the Xilinx® iMPACT software. In addition, the JTAG connector allows debug tools
such as the Vivado serial I/O analyzer or a software debugger to access the FPGA. The iMPACT
software tool can also indirectly program the Linear BPI Flash memory. To accomplish this, the
iMPACT software configures the FPGA with a temporary design to access and program the BPI
memory device.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
SPST Bus Switch SPST Bus Switch
U27 U28
N.C.
J35 J37
FMC1 HPC FMC2 HPC
Connector Connector
TDI TDO TDI TDO
Figure 1-7: JTAG Chain Block Diagram
www.xilinx.com
Figure 1-7. JTAG configuration is allowed at
N.C.
3.3V 1.8V
U46
SN74AVC1T45
Voltage
Translator
TDI TDO
U72
SN74AVC1T45
Voltage
Translator
TDO TDI
Feature Descriptions
U1
Kintex-7
FPGA
TDI
TDO
UG885_c1_07_021412
27
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