Xilinx VC707 User Manual page 60

VC707 Evaluation Board Features
Chapter 1:
The 10 x 40 rows of an FMC HPC connector provides pins for up to:
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The VC707 board FMC2 HPC connector J37 implements a subset of the maximum signal and clock
connectivity capabilities:
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The FMC2 HPC signals are distributed across GTX Quads 116 and 117. Each Quad has the VCCO
voltage connected to VADJ.
Note:
FMC VADJ power sequencing logic described in
Signaling Speed Ratings:
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Mechanical specifications:
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The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on a -3 dB
insertion loss point within a two-level signaling environment.
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160 single-ended or 80 differential user-defined signals
10 GTX transceivers
2 GTX clocks
4 differential clocks
159 ground and 15 power connections
58 differential user-defined pairs (as shipped with the Virtex-7 XC7VX485T-2FFG1761C
FPGA installed on the VC707 board, the FMC2 HB00-HB21 bus connections are not
supported. Refer to the Virtex-7 FPGA VC707 Evaluation Kit Master Answer Record in
Appendix G: References for more information).
34 LA pairs (LA00-LA33)
24 HA pairs (HA00-HA23)
8 GTX transceivers
2 GTX clocks
2 differential clocks
The VC707 board VADJ voltage for the FMC2 HPC (J37) connector is determined by the
Single-ended: 9 GHz (18 Gb/s)
Differential
• Optimal Vertical: 9 GHz (18 Gb/s)
• Optimal Horizontal: 16 GHz (32 Gb/s)
• High Density Vertical: 7 GHz (15 Gb/s)
Samtec SEAM/SEAF Series
1.27 mm x 1.27 mm (0.050" x 0.050") pitch
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FMC_VADJ Voltage Control.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019