Sgmii Gtx Transceiver Clock Generation; Usb-To-Uart Bridge - Xilinx VC707 User Manual

SGMII GTX Transceiver Clock Generation

[Figure
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125 MHz
LVDS clock from a 25 MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX
transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling
capacitors are present to allow the clock input of the FPGA to set the common mode voltage.
Figure 1-17
X-Ref Target - Figure 1-17
C300
18pF 50V
NPO
X3
25.00 MHz
2
R320
GND2
1.0MΩ 5%
C301
GND2
4
18pF 50V
NPO
GND_SGMIICLK GND_SGMIICLK
References
Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet
MAC Product Guide for Vivado Design Suite (PG051)
Ethernet MAC v4.5 User Guide (UG138)
The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the
Marvell website
The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell
website
For more information about the ICS844021 device, go to the Integrated Device Technology website
[Ref 22]

USB-to-UART Bridge

[Figure
The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which
allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707
Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The
CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into
the USB port on the VC707 board.
Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the
USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS),
and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These
drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications
application software (for example, TeraTerm) that runs on the host computer. The VCP device
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
1-2, callout 16]
shows the Ethernet SGMII clock source.
VDDA_SGMIICLK
1
X1 SGMIICLK_XTAL_OUT
3
X2 SGMIICLK_XTAL_IN
Figure 1-17: Ethernet 125 MHz SGMII GTX Clock
[Ref 21].
[Ref 21].
and search for part number ICS844021.
1-2, callout 17]
www.xilinx.com
VDD_SGMIICLK
U2
ICS844021I-01
Clock Generator
5
OE
8
1
VDDA VDD
7
3 SGMIICLK_Q0_C_P
XTAL_OUT Q0
6
4 SGMIICLK_Q0_C_N
XTAL_IN NQ0
2
GND
GND_SGMIICLK
[Ref 9] and in the LogiCORE IP Tri-Mode
[Ref 13].
Feature Descriptions
C28
0.1μF 25V
X5R
SGMIICLK_Q0_P
SGMIICLK_Q0_N
C29
0.1μF 25V
X5R
UG885_c1_17_020612
43
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