Configuration Options - Xilinx VC707 User Manual

VC707 Evaluation Board Features
Chapter 1:

Configuration Options

The FPGA on the VC707 board can be configured by the following methods:
•
•
See 7 Series FPGAs Configuration User Guide (UG470)
modes.
The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0) settings
selected through DIP switch SW11.
Table 1-34: Mode Switch SW11 Settings
Figure 1-36
X-Ref Target - Figure 1-36
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
The mode pins settings on SW11 determine if the Linear BPI Flash is used for configuring the
FPGA. DIP switch SW11 also provides the upper two address bits for the Linear BPI Flash and can
be used to select one of multiple stored configuration bitstreams.
between the onboard nonvolatile Flash devices used for configuration and the FPGA.
To obtain the fastest configuration speed an external 80 MHz oscillator is wired to the EMCCLK pin
of the FPGA. This allows users to create bitstreams that configure the FPGA over the 16-bit
datapath from the Linear BPI Flash memory at a maximum synchronous read rate of 80 MHz.
78
Send Feedback
Master BPI (uses the Linear BPI Flash).
JTAG (uses the USB-to-JTAG Bridge or Download cable). See
information
Mode Pins
Configuration Mode
(M2, M1, M0)
010
101
shows mode switch SW13.
R396 R398
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R397 R399
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
GND
Figure 1-36: Mode Switch
www.xilinx.com
[Ref 3]
Table 1-34 lists the supported mode switch settings.
Master BPI
JTAG
VCC2V5
SW11
ON
10 1
9 2
8 3
7 4
6 5
SDA05H1SBD
R400
1.21kΩ
0.1 W
1%
USB JTAG for more
for further details on configuration
R401 R402
220Ω 220Ω
0.1 W 0.1 W
1% 1%
UG885_c1_33_030512
Figure 1-37 shows the connectivity
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019