Xilinx VC707 User Manual page 34

VC707 Evaluation Board Features
Chapter 1:
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Table 1-11
Table 1-11:
Transceiver Bank
MGT_BANK_113
MGT_BANK_114
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Quad 113:
• MGTREFCLK0 - SGMII clock
• MGTREFCLK1 - SMA clock
• Contains 3 GTX transceivers with one each allocated to SMA, SGMII and SFP
• Contains 1 unused GTX transceiver
Quad 114:
• MGTREFCLK0 - Si5324 jitter attenuator
• Contains 4 GTX transceivers for PCIe ® lanes 4–7
Quad 115:
• MGTREFCLK1 - PCIe edge connector clock
• Contains 4 GTX transceivers for PCIe lanes 0–3
Quad 116:
• MGTREFCLK0 - FMC2 HPC GBTCLK1
• Contains 4 GTX transceivers for FMC2 HPC (DP4 – DP7)
• Quad 117:
• MGTREFCLK0 - FMC2 HPC GBTCLK0
• Contains 4 GTX transceivers for FMC2 HPC (DP0 – DP3)
Quad 118:
• MGTREFCLK0 - FMC1 HPC GBTCLK1
• Contains 4 GTX transceivers for FMC1 HPC (DP4 – DP7)
Quad 119:
• MGTREFCLK0 - FMC1 HPC GBTCLK0
• Contains 4 GTX transceivers for FMC1 HPC (DP0 – DP3)
lists the GTX interface connections to the FPGA (U1).
GTX Interface Connections for FPGA U1
FHG1761 Placement
GTXE2_CHANNEL_X1Y0
GTXE2_CHANNEL_X1Y1
GTXE2_CHANNEL_X1Y2
GTXE2_CHANNEL_X1Y3
MGTREFCLK0
MGTREFCLK1
GTXE2_CHANNEL_X1Y4
GTXE2_CHANNEL_X1Y5
GTXE2_CHANNEL_X1Y6
GTXE2_CHANNEL_X1Y7
MGTREFCLK0
MGTREFCLK1
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Connections
SMA
SGMII
SFP+
NC
SGMII_CLK
SMA_MGT_REFCLK
PCIe7
PCIe6
PCIe5
PCIe4
Si5324
NC
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019