Xilinx VC707 User Manual page 42

VC707 Evaluation Board Features
Chapter 1:
Table 1-17: Board Connections for PHY Configuration Pins
Pin Connection on Board
CFG0 V 2.5V
CC
CFG1 Ground
CFG2 V 2.5V
CC
CFG3 V 2.5V
CC
CFG4 V 2.5V
CC
CFG5 PHY_LED_LINK10
CFG6 PHY_LED_RX
The Ethernet connections from FPGA U1 to the 88E1111 PHY device are listed in
Table 1-18: Ethernet Connections, FPGA to PHY Device
FPGA (U1)
Net Name
Pin
AK33 PHY_MDIO
AH31 PHY_MDC
AL31 PHY_INT
AJ33 PHY_RESET
AN2 SGMII_TX_P
AN1 SGMII_TX_N
AM8 SGMII_RX_P
AM7 SGMII_RX_N
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Bit[2]
Definition and Value
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
ANEG[0] = 1
HWCFG_MD[2] = 1
DIS_FC = 1
SEL_BDT = 0
I/O Standard
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
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Bit[1]
Definition and Value
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
ENA_XC = 1
HWCFG_MD[1] = 1
DIS_SLEEP = 1
INT_POL = 1
M88E1111 PHY U50
Pin
M1
L3
L1
K3
A3
A4
A7
A8
UG885 (v1.8) February 20, 2019
Bit[0]
Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
HWCFG_MD[3] = 1
75/50Ω= 0
Table 1-18.
Name
MDIO
MDC
INT_B
RESET_B
SIN_P
SIN_N
SOUT_P
SOUT_N
VC707 Evaluation Board