Xilinx VC707 User Manual page 67

Table 1-28: J37 VITA 57.1 FMC 2 HPC Connections (Cont'd)
J37
FMC 2
Schematic Net Name
HPC
Pin
C2 FMC2_HPC_DP0_C2M_P
C3 FMC2_HPC_DP0_C2M_N
C6 FMC2_HPC_DP0_M2C_P
C7 FMC2_HPC_DP0_M2C_N
C10 FMC2_HPC_LA06_P
C11 FMC2_HPC_LA06_N
C14 FMC2_HPC_LA10_P
C15 FMC2_HPC_LA10_N
C18 FMC2_HPC_LA14_P
C19 FMC2_HPC_LA14_N
C22 FMC2_HPC_LA18_CC_P
C23 FMC2_HPC_LA18_CC_N
C26 FMC2_HPC_LA27_P
C27 FMC2_HPC_LA27_N
C30 FMC2_HPC_IIC_SCL
C31 FMC2_HPC_IIC_SDA
C34 GA0 = 0 = GND
C35 VCC12_P
C37 VCC12_P
C39 VCC3V3
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
I/O U1 FPGA FMC 2
Standard Pin HPC
(1)
N2 D1
(1)
N1 D4
(1)
P8 D5
(1) P7 D8
AD38 D9
LVCMOS18
AE38 D11
LVCMOS18
AB41 D12
LVCMOS18
AB42 D14
LVCMOS18
AB38 D15
LVCMOS18
AB39 D17
LVCMOS18
U36 D18
LVCMOS18
T37 D20
LVCMOS18
P32 D21
LVCMOS18
P33 D23
LVCMOS18
U52.6 D24
U52.5 D26
D27
D29
D30
D31
D32
D33
D34
D35
D36
D38
D40
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J37
Schematic Net Name
Pin
PWRCTL1_VCC4B_PG
FMC2_HPC_GBTCLK0_M2C_P
FMC2_HPC_GBTCLK0_M2C_N
FMC2_HPC_LA01_CC_P
FMC2_HPC_LA01_CC_N
FMC2_HPC_LA05_P
FMC2_HPC_LA05_N
FMC2_HPC_LA09_P
FMC2_HPC_LA09_N
FMC2_HPC_LA13_P
FMC2_HPC_LA13_N
FMC2_HPC_LA17_CC_P
FMC2_HPC_LA17_CC_N
FMC2_HPC_LA23_P
FMC2_HPC_LA23_N
FMC2_HPC_LA26_P
FMC2_HPC_LA26_N
FMC2_HPC_TCK_BUF
FMC1_TDO_FMC2_TDI
FMC2_TDO_FPGA_TDI
VCC3V3
FMC2_HPC_TMS_BUF
NC
GA1 = 0 = GND
VCC3V3
VCC3V3
VCC3V3
Feature Descriptions
I/O U1 FPGA
Standard Pin
AL32
(1)
K8
(1)
K7
AF41
LVCMOS18
AG41
LVCMOS18
AF42
LVCMOS18
AG42
LVCMOS18
AJ38
LVCMOS18
AK38
LVCMOS18
W40
LVCMOS18
Y40
LVCMOS18
U37
LVCMOS18
U38
LVCMOS18
R38
LVCMOS18
R39
LVCMOS18
N33
LVCMOS18
N34
LVCMOS18
U19.13
U27.2
U46.3
U19.16
67
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