Xilinx VC707 User Manual page 58

VC707 Evaluation Board Features
Chapter 1:
X-Ref Target - Figure 1-31
Configuration Mode and Upper Linear Flash Address Switch (SW11)
[Figure
FPGA Configuration Mode: DIP switch SW11 positions 3, 4, and 5 control which configuration
mode is used at power-up or when the PROG pushbutton is pressed.
Linear BPI Flash Upper Addresses: DIP switch SW11 positions 1 and 2 control the setting of
address bits FLASH_A25 and FLASH_A24. The mode signals FPGA_M2, _M1 and _M0 are
connected to FPGA U1 pins AJ10, AK10 and AL10 respectively. Configuration mode is used at
power-up or when the PROG pushbutton is pressed.
Figure 1-32
X-Ref Target - Figure 1-32
58
Send Feedback
FPGA_PROG_B
Figure 1-31: FPGA_PROG_B Pushbutton SW9
1-2, callout 29]
shows the SW11 circuit.
FLASH_A25
FLASH_A24
FPGA_M2
FPGA_M1
FPGA_M0
R341
1.21kΩ
0.1 W
1%
R340
1.21kΩ
0.1 W
1%
GND
Figure 1-32: Configuration Mode and Upper Linear Flash Address Switch
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VCC1V9
R42
4.7kΩ
0.1 W
5%
SW9
1 4
2 3
UG885_c1_28_030512
VCC1V8
SW11
10 1
9 2
8 3
7 4
6 5
SDA05H1SBD
R339 R337
1.21kΩ 1.21kΩ
0.1 W 0.1 W
1% 1%
R338
1.21kΩ
0.1 W
1%
UG885 (v1.8) February 20, 2019
GND
R226 R227
220Ω 220Ω
0.1 W 0.1 W
1% 1%
UG885_c1_29_030512
VC707 Evaluation Board