Xilinx VC707 User Manual page 18

VC707 Evaluation Board Features
Chapter 1:
Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
FPGA (U1) Pin
D30
M13
K15
F12
A14
C23
D25
C31
F31
M16 DDR3_DQS0_N
N16 DDR3_DQS0_P
J12 DDR3_DQS1_N
K12 DDR3_DQS1_P
G16 DDR3_DQS2_N
H16 DDR3_DQS2_P
C14 DDR3_DQS3_N
C15 DDR3_DQS3_P
A27 DDR3_DQS4_N
A26 DDR3_DQS4_P
E25 DDR3_DQS5_N
F25 DDR3_DQS5_P
B29 DDR3_DQS6_N
B28 DDR3_DQS6_P
E28 DDR3_DQS7_N
E27 DDR3_DQS7_P
H20 DDR3_ODT0
H18 DDR3_ODT1
C29 DDR3_RESET_B
J17
J20
G17 DDR3_TEMP_EVENT
F20 DDR3_WE_B
18
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Net Name
DDR3_D63
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_DM4
DDR3_DM5
DDR3_DM6
DDR3_DM7
DDR3_S0_B
DDR3_S1_B
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I/O Standard
Pin Number
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
DIFF_SSTL15
SSTL15
SSTL15
LVCMOS15
SSTL15
SSTL15
SSTL15
SSTL15
J1 DDR3 Memory
Pin Name
194 DQ63
11 DM0
28 DM1
46 DM2
63 DM3
136 DM4
153 DM5
170 DM6
187 DM7
10 DQS0_N
12 DQS0_P
27 DQS1_N
29 DQS1_P
45 DQS2_N
47 DQS2_P
62 DQS3_N
64 DQS3_P
135 DQS4_N
137 DQS4_P
152 DQS5_N
154 DQS5_P
169 DQS6_N
171 DQS6_P
186 DQS7_N
188 DQS7_P
116 ODT0
120 ODT1
30 RESET_B
114 S0_B
121 S1_B
198 EVENT_B
113 WE_B
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019