Xilinx VC707 User Manual page 3

Date Version
02/01/13 1.2
08/22/13 1.3
05/12/14 1.4
09/20/14 1.5
04/07/15 1.6
09/01/15 1.6.1
03/26/16 1.7
08/12/16 1.7.1
02/20/19 1.8
UG885 (v1.8) February 20, 2019
Updated VC707 Board Features,
Configuration, USB JTAG, System Clock (SYSCLK_P and
2C Bus
I , Table 1-15, User I/O,
Connector (Partially Populated). Updated
paragraph following Table 1-4,
Reset Pushbutton, User Rotary
System Cooling. Added Table 1-27
PTD08D210W in Table 1-29. Added third paragraph to the introduction in
Constraints File. Added UG483 and removed NXP Semiconductors in
Resources. Added second paragraph to the introduction in
Compliance Information.
Updated Figure 1-2, Table 1-1,
Memory. Replaced Master UCF Listing with
Updated disclaimer and copyright. In
A35, and B37 to A36.
Added note to Table 1-1 and Table
to FHG1761 Placement in Table
Table 1-8, Table 1-10, Table 1-18,
Updated schematic net name for pins C34 and D35 in
Transceivers. Added Figure A-3.
Added notes to Jitter Attenuated Clock
Figure B-2 FMC2 HPC Connector Pinout in
Added information for ordering the ATX power supply adapter cable.
Made typographical edits.
Updated transceiver bank MGT_BANK_119 in
pushbutton switch in Table 1-26. Updated U1 FPGA pins for J37 FMC2 HPC pins B12, B13, B32,
and B33 in Table 1-28. Added thickness information in
Made a typographical edit.
Added the latest version of ESD Directive in
the description of Chapter 1, DDR3
Table 1-28. In Appendix C, Xilinx Constraints File
description and removed the VC707 Board XDC Listing. Updated
Compliance Information. Updated
www.xilinx.com
Revision
Table 1-1, Virtex-7 XC7VX485T-2FFG1761C
Table 1-26, Power Management, and
Figure 1-5, Figure
Figure 1-7, Figure 1-19, Figure
Switch, User SMA, and PCIe Form Factor Board TI Power
and Table 1-28. Replaced PTD08D021W with
Appendix F, Regulatory and
Table 1-12, Table 1-13, and
Appendix C, Xilinx Constraints
Table 1-27, changed U1 FPGA pin N39 to M39, B36 to
1-27. Updated Table 1-7. Changed Net Name column heading
1-11. Added I/O standard information to
Table 1-21, Table 1-23, Table
Table 1-27
2C Bus
and I . Updated
Appendix B, VITA 57.1 FMC Connector
Table 1-11. Updated GPIO pin for CPU reset
Appendix E, Board
Chapter 1, Electrostatic Discharge
Memory. Updated the U1 FPGA Pin for F31 and F32 in
changed the title of the appendix, updated the
Appendix G, References
FPGA,
SYSCLK_N), HDMI Video
VITA 57.1 FMC2 HPC
1-16, and Figure 1-25. Updated
1-20, and Table 1-24. Added
Appendix C, Xilinx
Appendix G, Additional
Table 1-14. Updated Linear BPI Flash
File.
Table 1-4, Table
1-26, Table 1-27 and Table
and Table 1-28. Updated
Table 1-24. Deleted redundant
Pinouts.
Specifications.
Caution. Updated
Appendix F, Regulatory and
VC707 Evaluation Board
FPGA
Output,
CPU
1-5,
1-28.
GTX