Jtag Test-Port Timing - Texas Instruments TMS320C6712D User Manual

timing requirements for JTAG test port (see Figure 49)
NO. NO.
1 t c(TCK) Cycle time, TCK
3 t su(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high
4 t h(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 49)
NO. NO.
2 t d(TCKL-TDOV) Delay time, TCK low to TDO valid
TCK
TDO
TDI/TMS/TRST
FLOATING POINT DIGITAL SIGNAL PROCESSOR

JTAG TEST-PORT TIMING

PARAMETER PARAMETER
1
2
Figure 49. JTAG Test-Port Timing
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
SPRS293 − OCTOBER 2005
4
3
TMS320C6712D
−150
UNIT UNIT
MIN MAX
35 ns
10 ns
7 ns
−150
UNIT UNIT
MIN MAX
0 15 ns
2
97