Hold/Holda Timing - Texas Instruments TMS320C6712D User Manual

timing requirements for the HOLD/HOLDA cycles
NO. NO.
3 t h(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low
† E = ECLKIN period in ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
(see Figure 37)
NO. NO.
1 t d(HOLDL-EMHZ)
2 t d(EMHZ-HOLDAL)
4 t d(HOLDH-EMLZ)
5 t d(EMLZ-HOLDAH)
† E = ECLKIN period in ns
‡ EMIF Bus consists of CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus †
† EMIF Bus consists of CE[3:0], BE[1:0], ED[15:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
FLOATING POINT DIGITAL SIGNAL PROCESSOR

HOLD/HOLDA TIMING

PARAMETER PARAMETER
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to HOLDA high
External Requestor
DSP Owns Bus
2
1
C6712D
Figure 37. HOLD/HOLDA Timing
POST OFFICE BOX 1443
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
†
(see Figure 37)
Owns Bus
3
4
•
HOUSTON, TEXAS 77251−1443
TMS320C6712D
−150
UNIT UNIT
MIN MAX
E
−150
UNIT UNIT
MIN MAX
§
2E
0 2E
2E 7E
0 2E
DSP Owns Bus
5
C6712D
ns
†‡
ns
ns
ns
ns
81