Electrical Characteristics Over Recommended Ranges Of Supply Voltage And Operating Case Temperature; Test Conditions - Texas Instruments TMS320C6712D User Manual

TMS320C6712D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
electrical characteristics over recommended ranges of supply voltage and operating case
†
temperature (unless otherwise noted)
PARAMETER
High-level output
V OH
voltage
Low-level output
V OL V OL
voltage voltage
I I I I Input current Input current
Off-state output
I OZ I OZ
current current
I DD2V Core supply current ‡
I DD3V I/O supply current ‡
C i Input capacitance
C o Output capacitance
† For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡ For more details on CPU, peripheral, and I/O activity, see the TMS320C62x/C67x Power Consumption Summary application report (literature
number SPRA486).
For the device, these currents were measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF.
This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity
operations. The high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D/12D/13B Power
Consumption Summary application report (literature number SPRA889A).
62
All signals except CLKS1 and
DR1
All signals except CLKS1 and
DR1
CLKS1 and DR1
All signals except CLKS1 and
DR1
CLKS1 and DR1
All signals except CLKS1 and
DR1
CLKS1 and DR1
C6712D
C6712D
•
POST OFFICE BOX 1443

TEST CONDITIONS

DV DD = MIN, I OH = MAX
DV DD = MIN, I OL = MAX DV DD = MIN, I OL = MAX
V I = V SS to DV DD V I = V SS to DV DD
V O = DV DD or 0 V V O = DV DD or 0 V
CV DD = 1.26 V, CPU
clock = 150 MHz
DV DD = 3.3 V,
EMIF speed = 100 MHz
HOUSTON, TEXAS 77251−1443
MIN TYP MAX
2.4
0.4
0.4
±170
±10
±170
±10
430
75
7
7
UNIT
V
V
V
uA
uA
uA
uA
mA
mA
pF
pF