Texas Instruments TMS320C6712D User Manual page 89

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 42)
NO. NO.
1 t su(FRH-CKSH) Setup time, FSR high before CLKS high
2 t h(CKSH-FRH) Hold time, FSR high after CLKS high
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
NO. NO.
4 t su(DRV-CKXL) Setup time, DR valid before CLKX low
5 t h(CKXL-DRV) Hold time, DR valid after CLKX low
† P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
CLKS
Figure 42. FSR Timing When GSYNC = 1
POST OFFICE BOX 1443
FLOATING POINT DIGITAL SIGNAL PROCESSOR
1
2
MASTER
MIN
•
HOUSTON, TEXAS 77251−1443
TMS320C6712D
SPRS293 − OCTOBER 2005
−150
MIN MAX
4
4
†‡
(see Figure 43)
−150
SLAVE
MAX MIN MAX
12 2 − 6P
4 5 + 12P
UNIT UNIT
ns
ns
UNIT UNIT
ns
ns
89