Texas Instruments TMS320C6712D User Manual page 51

PLL and PLL controller (continued)
PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers
(0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively)
28
31
14
15 12
DxEN
R/W−1
Legend: R = Read only, R/W = Read/Write; -n = value after reset
† Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.
D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.
Table 30. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1,
BIT # NAME
31:16 Reserved
15 DxEN
14:5 Reserved
4:0 PLLDIVx
‡ Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example,
if D1 is set to /2, then D2 must be set to /4.
27 24 23
11 8
Reserved
R−0
CAUTION:
D2, and D3)
Reserved. Read-only, writes have no effect.
Divider Dx Enable (where x denotes 0 through 3).
0 – Divider x Disabled. No clock output.
1 – Divider x Enabled (default).
These divider-enable bits are device-specific and must be set to 1 to enable.
Reserved. Read-only, writes have no effect.
PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1,
/2, and /2, respectively].
00000 = /1
00001 = /2
00010 = /3
00011 = /4
00100 = /5
00101 = /6
00110 = /7
00111 = /8
01000 = /9
01001 = /10
01010 = /11
01011 = /12
01100 = /13
01101 = /14
01110 = /15
01111 = /16
POST OFFICE BOX 1443
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
20 19
Reserved
R−0
7 5 4
‡
DESCRIPTION
10000 = /17
10001 = /18
10010 = /19
10011 = /20
10100 = /21
10101 = /22
10110 = /23
10111 = /24
11000 = /25
11001 = /26
11010 = /27
11011 = /28
11100 = /29
11101 = /30
11110 = /31
11111 = /32
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HOUSTON, TEXAS 77251−1443
TMS320C6712D
3 2 1
PLLDIVx
R/W−x xxxx †
16
0
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