Texas Instruments TMS320C6712D User Manual page 29

PIN
NO.
SIGNAL SIGNAL
NAME
GDP/
ZDP
CLKS0 K3
CLKR0 H3
CLKX0 G3
DR0 J1
DX0 H2
FSR0 J3
FSX0 H1
CLKOUT2/GP[2] Y12
GP[7](EXT_INT7) E3
GP[6](EXT_INT6) D2
GP[5](EXT_INT5) C1
GP[4](EXT_INT4) C2
RSV C12
RSV D12
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
Terminal Functions (Continued)
IPD/ IPD/
TYPE † TYPE †
IPU ‡ ‡
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
I IPD External clock source (as opposed to internal)
I/O/Z IPD Receive clock
I/O/Z IPD Transmit clock
I IPU Receive data
O/Z IPU Transmit data
I/O/Z IPD Receive frame sync
I/O/Z IPD Transmit frame sync
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) MODULE
Clock output at half of device speed
For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin. Clock output at half of
I/O/Z IPD
device speed (O/Z) [default] (SYSCLK2 internal signal
from the clock generator) or this pin can be programmed as GP[2] (I/O/Z).
External interrupts
• Edge-driven
Edge-driven
• Polarity independently selected via the External Interrupt Polarity Register
Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0])
I/O/Z I/O/Z IPU IPU
General-purpose input/output pins (I/O/Z) which also function as external
interrupts
• Edge-driven • Edge-driven
• Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0]), in addition to the GPIO registers.
RESERVED FOR TEST
O − Reserved (leave unconnected, do not connect to power or ground)
For proper device operation, the D12 pin must be externally pulled down with a 10-kΩ re-
I −
sistor.
POST OFFICE BOX 1443
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
DESCRIPTION DESCRIPTION
•
HOUSTON, TEXAS 77251−1443
TMS320C6712D
29