Cpu Csr Register Description - Texas Instruments TMS320C6712D User Manual

TMS320C6712D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

CPU CSR register description

The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the
status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the
endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 6 and
Table 17 identify the bit fields in the CPU CSR register.
For more detailed information on the bit fields in the CPU CSR register, see the TMS320C6000 DSP Peripherals
Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set
Reference Guide (literature number SPRU189).
31
CPU ID
R-0x02
15
PWRD
R/W-0
Legend:
R = Readable by the MVC instruction, R/W = Readable/Writeable by the MVC instruction; W = Read/write; -n = value after reset, -x = undefined value after
reset, C = Clearable by the MVC instruction
40
24 23
10 9 8 7
SAT EN
R/C-0 R-1
Figure 6. CPU Control Status Register (CPU CSR)
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REVISION ID
R-0x03
6 5 4
PCC DCC
R/W-0 R/W-0
16
2 1 0
PGIE GIE
R/W-0 R/W-0