Texas Instruments TMS320C6712D User Manual page 26

TMS320C6712D
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
PIN
NO.
SIGNAL SIGNAL
TYPE † TYPE †
NAME
GDP/
ZDP
RESET A13 I
NMI C13 I
EXT_INT7 E3
EXT_INT6 D2
I I
EXT_INT5 C1
EXT_INT4 C2
CE3 V6 O/Z
CE2 W6 O/Z
CE1 W18 O/Z
CE0 V17 O/Z
BE1 U19 O/Z
BE0 V20 O/Z
HOLDA J18 O
HOLD J17 I
BUSREQ J19 O
EMIF − ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL #
ECLKIN Y11 I
ECLKOUT Y10 O
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
# To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
26
Terminal Functions (Continued)
IPD/ IPD/
IPU ‡ ‡
RESETS AND INTERRUPTS
Device reset. When using Boundary Scan mode on the device, drive the EMU[1:0] and RESET
−− pins low.
This pin does not have an IPU.
Nonmaskable interrupt
• Edge-driven (rising edge)
IPD
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is
recommended that the NMI pin be grounded versus relying on the IPD.
General-purpose input/output pins (I/O/Z) which also function as external interrupts (default) General-purpose input/output pins (I/O/Z) which also function as external interrupts (default)
• Edge-driven • Edge-driven
IPU IPU
• Polarity independently selected via the External Interrupt Polarity Register
Polarity independently selected via the External Interrupt Polarity Register
bits (EXTPOL.[3:0]), in addition to the GPIO registers. bits (EXTPOL.[3:0]), in addition to the GPIO registers.
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY #
IPU
Memory space enables Memory space enables
IPU
• Enabled by bits 28 through 31 of the word address • Enabled by bits 28 through 31 of the word address
IPU
• Only one asserted during any external data access • Only one asserted during any external data access
IPU
Byte-enable control
IPU
• Decoded from the two lowest bits of the internal address • Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory
IPU
• Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF − BUS ARBITRATION #
IPU Hold-request-acknowledge to the host
IPU Hold request from the host
IPU Bus request output
IPD EMIF input clock
EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit
(GBLCTL.[5])
EKSRC = 0 – ECLKOUT is based on the internal SYSCLK3 signal
from the clock generator (default).
IPD EKSRC = 1 – ECLKOUT is based on the the external EMIF input clock
source pin (ECLKIN)
EKEN = 0 – ECLKOUT held low
EKEN = 1 – ECLKOUT enabled to clock (default)
•
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