Texas Instruments TMS320C6712D User Manual page 93

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
FSX
6
DX Bit 0
DR Bit 0
Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1
NO. NO.
4 t su(DRV-CKXH) Setup time, DR valid before CLKX high
5 t h(CKXH-DRV) Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1
NO. NO.
Hold time, FSX low
1 t h(CKXH-FXL)
after CLKX high ¶
Delay time, FSX low to CLKX low #
2 t d(FXL-CKXL)
3 t d(CKXH-DXV) Delay time, CLKX high to DX valid
Disable time, DX high impedance following last data bit from
6 t dis(CKXH-DXHZ)
CLKX high
7 t d(FXL-DXV) Delay time, FSX low to DX valid
† P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
FLOATING POINT DIGITAL SIGNAL PROCESSOR
2
7
8
4
†‡
(see Figure 46)
PARAMETER PARAMETER
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
3
Bit(n-1) (n-2) (n-3)
5
Bit(n-1) (n-2) (n-3)
MASTER
MIN MAX
12
4
MASTER §
MIN MAX
H − 2 H + 3
T − 2 T + 3
−3
−2
L − 2 L + 6.5
TMS320C6712D
SPRS293 − OCTOBER 2005
(n-4)
(n-4)
†‡
(see Figure 46)
−150
SLAVE
UNIT UNIT
MIN MAX
2 − 6P ns
5 + 12P ns
−150
SLAVE
UNIT UNIT
MIN MAX
ns
ns
4 6P + 2 10P + 17 ns
4 6P + 3 10P + 17 ns
4P + 2 8P + 17 ns
93